High performance two-port SRAM architecture using 8T high performance single port bit cell

Abstract

An 8T memory bit cell receives a clock signal and read and write address signals. A read address latch/clock circuit receives the clock signal and the read address signals and initiates a read operation during a first clock cycle state. A write address flip-flop/clock circuit receives the clock signal and the write address signals and initiates a write operation during a second clock cycle state. An inverter receives and inverts the clock signal and applies the inverted clock signal to the write address flip-flop/clock circuit. The read address latch/clock circuit initiates a read word line precharge operation during the second clock cycle state and a write word line precharge operation during the first clock cycle state. The write address flip-flop/clock circuit may also include a loose self-timer to end a write cycle is a clock signal continues beyond a predetermined time.

The invention claimed is: 
     
       1. An 8T memory bit cell for connection to receive a clock signal and read and write address signals, comprising:
 a read word line; 
 a write word line; 
 a read address latch/clock circuit for receiving said clock signal and said read address signals to initiate a read operation during a first clock cycle state; 
 a write address flip-flop/clock circuit for receiving said clock signal and said write address signals to initiate a write operation during a second clock cycle state; and 
 an inverter for receiving and inverting said clock signal and for applying said inverted clock signal to said write address flip-flop/clock circuit; 
 wherein said read address latch/clock circuit initiates a read word line precharge operation during said second clock cycle state and write address flip-flop/clock circuit initiates a write word line precharge operation during said first clock cycle state. 
 
     
     
       2. The 8T memory bit cell of  claim 1  wherein said first clock cycle state is a high clock cycle state and said second clock cycle state is a low clock cycle state. 
     
     
       3. The 8T memory bit cell of  claim 1  wherein said high and low clock states occur within a single clock cycle. 
     
     
       4. The 8T memory bit cell of  claim 1  wherein said write address flip-flop/clock circuit comprises a loose self-timer, wherein if said low clock cycle state continues beyond a first predetermined time, said loose self-timer ends said write operation at a second predetermined time less than said first predetermined time. 
     
     
       5. A memory array, comprising:
 a plurality of 8T memory bit cells, each for connection to receive a clock signal and read and write address signals, each 8T memory bit cell comprises:
 a read word line; 
 a write word line; 
 a read address latch/clock circuit for receiving said clock signal and said read address signals to initiate a read operation during a first clock cycle state; 
 a write address flip-flop/clock circuit for receiving said clock signal and said write address signals to initiate a write operation during a second clock cycle state; and 
 an inverter for receiving and inverting said clock signal and for applying said inverted clock signal to said write address flip-flop/clock circuit; 
 wherein said read address latch/clock circuit initiates a read word line precharge operation during said second clock cycle state and write address flip-flop/clock circuit initiates a write word line precharge operation during said first clock cycle state. 
 
 
     
     
       6. The memory array of  claim 5  wherein said first clock cycle state is a high state and said second clock cycle state is a low state. 
     
     
       7. The memory array of  claim 6  wherein said high and low clock states occur within a single clock cycle. 
     
     
       8. The memory array of  claim 7  wherein said read and write operations occur during said single clock cycle. 
     
     
       9. The memory array of  claim 8  wherein said read operation occurs during a high phase of said single clock cycle and said write operation occurs during a low phase of said single clock cycle. 
     
     
       10. A memory array, comprising:
 a plurality of 8T memory bit cells, each for connection to receive a clock signal and read and write address signals, each 8T memory bit cell comprises:
 a read word line; 
 a write word line; 
 a read address latch/clock circuit for receiving said clock signal and said read address signals to initiate a read operation during a first clock cycle state; and 
 a write address flip-flop/clock circuit for receiving said clock signal and said write address signals to initiate a write operation during a second clock cycle state; 
 wherein said write address flip-flop/clock circuit comprises a loose self-timer, wherein if said low clock cycle state continues beyond a first predetermined time, said loose self-timer facility ends said write operation at a second predetermined time less than said first predetermined time. 
 
 
     
     
       11. A method for operating an 8T memory bit cell, comprising:
 applying a clock signal to said 8T memory bit cell, said clock signal having a first and second clock cycle states; 
 performing a read operation during said first clock state; 
 performing a write operation during said second clock state; and 
 
       operating said read address latch/clock circuit to perform a read word line precharge operation during said second clock state and operating said write address flip-flop/clock circuit to perform a write word line precharge operation during said first clock state. 
     
     
       12. The method of  claim 11  wherein said first clock state is a high state and said second clock state is a low state. 
     
     
       13. A method for operating an 8T memory bit cell, comprising:
 applying a clock signal to said 8T memory bit cell, said clock signal having a first and second clock cycle states; 
 performing a read operation during said first clock state; 
 performing a write operation during said second clock state; and 
 
       providing a read address latch/clock circuit and a corresponding read word line, and a write address flip-flop/clock circuit and a corresponding write word line, wherein said applying said clock signal to said 8T memory bit cell comprises applying said clock signal to said read address latch/clock circuit and said write address flip-flop/clock circuit. 
     
     
       14. The method of  claim 12  further comprising inverting said clock signal before said clock signal is applied to said write address flip-flop/clock circuit. 
     
     
       15. The method of  claim 12  further comprising providing loose self-timing wherein if said low state continues beyond a first predetermined time, said loose self-timing ends said write operation at a second predetermined time less than said first predetermined time.