Inventor

TING TAH-KANG JOSEPH

TW35 patents

⚠️ This page may combine multiple inventors who share the name “TING TAH-KANG JOSEPH”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

TING TAH-KANG JOSEPH

ETRON TECHNOLOGY INC

Internal power management scheme for a memory chip in deep power down mode

Partial refresh feature in pseudo SRAM

High efficiency CMOS pump circuit

Internal power management scheme for a memory chip in deep power down mode

Input buffer with compensation for process variation

Low power SRAM redundancy repair scheme

Level boost restoration circuit

Mixed mode output buffer circuit for CMOSIC

DRAM refresh scheme with flexible frequency for active and standby mode

Design for testability in very high speed memory

Flexible time write operation

High speed programmable burst address generation circuit

Integrated circuit chip having multiple package options

Method of high speed data rate testing

Noise reduction method and system for a multiple clock, mixed signal integrated circuit

Protection circuit to ensure DRAM signal in write cycle

Ping-pong boost circuit

tRAS protection circuit

Semiconductor memory arrays

High speed glitch-free transition detection circuit with disable control

Low standby power redundancy circuit

LCD controller which supports a no-scaling image without a frame buffer

Efficiency improvement in charge pump system for low power application

Distributed bit switch logically interleaved for block write performance

Method of high speed data rate testing

PIECEMAKERS TECH INC

Apparatus for enhancing prefetch access in memory module

DRAM with inter-section, page-data-copy scheme for low power and wide data access

DRAM with inter-section, page-data-copy scheme for low power and wide data access

Method for controlling memory device asynchronously with respect to system clock, and related memory device and memory system

Multi-bank memory device and system

Memory architecture dividing memory cell array into independent memory banks

Memory architecture with multi-bank memory cell array accessed by local drive circuit within memory bank

MEGIC CORP

Methods of IC rerouting option for multiple package system applications

MEGICA CORP

Semiconductor chip with redistribution metal layer

TING TAH-KANG JOSEPH

Memory cell and memory array utilizing the memory cell