Inventor

SCHAEFER SCOTT E

US106 patents

⚠️ This page may combine multiple inventors who share the name “SCHAEFER SCOTT E”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

SCHAEFER SCOTT E

MICRON TECHNOLOGY INC

Method for providing synchronous refresh cycles in self-refreshing interruptable DRAMs

Memory device operable in either a high-power, full-page size mode or a low-power, reduced-page size mode

Circuit for synchronizing refresh cycles in self-refreshing drams having timing circuit shutdown

Circuit for providing synchronous refresh cycles in self-refreshing interruptable DRAMs

Internal error correction for memory devices

Individually addressing memory devices disconnected from a data bus

Memory device operable in either a high-power, full-page size mode or a low-power, reduced-page size mode

Error correction memory device with fast data access

Command address fault detection using a parity pin

Error log indication via error control information

Real time syndrome check

Indicating a status of a memory built-in self-test for multiple memory device ranks

Techniques for detecting a state of a bus

Techniques for detecting a state of a bus

Techniques for indicating a write link error

Coordinated error protection

Coordinated error correction

Memory device with status feedback for error correction

Extended error detection for a memory device

Command block management

Refresh counters in a memory system

Individually addressing memory devices disconnected from a data bus

Internal error correction for memory devices

Memory device with status feedback for error correction

Targeted command/address parity low lift

Methods and devices for error correction

Error correction management for a memory device

Memory device with configurable error correction modes

Extended error detection for a memory device

Row hammer protection for a memory device

Individually addressing memory devices disconnected from a data bus

Individually addressing memory devices disconnected from a data bus

Method for synchronizing refresh cycles in self-refreshing DRAMs having timing circuit shutdown

Evaluation of memory device health monitoring logic

Temperature monitoring for memory devices

Monitoring and adjusting access operations at a memory device

Adaptive user defined health indication

Refresh rate selection for a memory built-in self-test

Managing error control information using a register

Coordinated error protection

Techniques for indicating a write link error

Techniques for detecting a state of a bus

Techniques for detecting a state of a bus

Error correction memory device with fast data access

Indicating a status of a memory built-in self-test for multiple memory device ranks

Indicating valid memory access operations

LODESTAR LICENSING GROUP LLC

Coordinated error correction

Internal error correction for memory devices

Methods and devices for error correction

Individually addressing memory devices disconnected from a data bus