Inventor

YUN WON-JOO

KR61 patents

⚠️ This page may combine multiple inventors who share the name “YUN WON-JOO”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

YUN WON-JOO

HYNIX SEMICONDUCTOR INC

DLL circuit and method of controlling the same

DLL circuit having duty cycle correction and method of controlling the same

Semiconductor memory apparatus

Data output strobe signal generating circuit and semiconductor memory apparatus having the same

Delay-locked loop apparatus and delay-locked method

Semiconductor integrated circuit

Power-down mode control apparatus and DLL circuit having the same

Delay locked loop apparatus

Semiconductor memory device for generating a delay locked clock in early stage

DLL circuit and method of controlling the same

Power-down mode control apparatus and DLL circuit having the same

Semiconductor memory apparatus with a delay locked loop circuit

Semiconductor memory device

Phase synchronization apparatus

Power control circuit, method of controlling power control circuit, and DLL circuit including power control circuit

Circuit and method for correcting duty cycle

Semiconductor memory device for generating a delay locked clock in early stage

Semiconductor integrated circuit and method of controlling the same

Update control apparatus in DLL circuit

Circuit and method for correcting duty cycle

DLL circuit and method of controlling the same

Apparatus and method of setting test mode in semiconductor integrated circuit

Apparatus and method of setting operation mode in DLL circuit

Duty cycle correcting circuit

Delay circuit of delay locked loop having single and dual delay lines and control method of the same

MICRON TECHNOLOGY INC

Apparatus including reconfigurable interface and methods of manufacturing the same

Apparatus including reconfigurable interface and methods of manufacturing the same

Data input buffer with a branched DFE reset path

Synchronous input buffer enable for DFE operation

Apparatuses, systems, and methods for ZQ calibration

Hybrid loop unrolled decision feedback equalizer architecture

Signal delay control and related apparatuses, systems, and methods

Methods for improving timing in memory devices, and related devices and systems

Test input/output speed conversion and related apparatuses and methods

SAMSUNG ELECTRONICS CO LTD

Memory device for performing calibration operation

Electronic device having a delay locked loop, and memory device having the same

Short circuit detecting device of stacked memory chips and method thereof

Duty cycle error detection device and duty cycle correction device having the same

Input-output circuit for supporting multiple-input shift register (MISR) function and memory device including the same

Semiconductor memory device including a shift register

Input buffer and memory device including the same

Memory package and memory device utilizing an intermediate chip

YUN WON JOO

DLL circuit having activation points

Power control circuit, method of controlling power control circuit, and DLL circuit including power control circuit

Power control circuit, method of controlling power control circuit, and DLL circuit including power control circuit

Delay locked loop apparatus

LEE HYUN WOO

Phase synchronization apparatus

Semiconductor integrated circuit having delay locked loop circuit

KIM KI HAN

Internal voltage generation circuit for semiconductor apparatus

YUN WON-JOO

Duty cycle correcting circuit and method of correcting a duty cycle