Inventor

PRALL KIRK D

US131 patents

⚠️ This page may combine multiple inventors who share the name “PRALL KIRK D”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

PRALL KIRK D

MICRON TECHNOLOGY INC

Band-engineered multi-gated non-volatile memory device with enhanced attributes

Multi-layer memory arrays

Programming methods for multi-level flash EEPROMs

Method of forming contact areas between vertical conductors

Plug-based floating gate memory

Memory cells

Low resistance gate flash memory

Low resistance gate flash memory

NROM memory cell, memory array, related devices and methods

Programming methods for multi-level flash EEPROMS

Method and apparatus for a flash memory device comprising a source local interconnect

Insulating materials

Method of forming materials between conductive electrical components, and insulating materials

Etch process for aligning a capacitor structure and an adjacent contact corridor

Flash memory cell having antimony drain for reduced drain voltage during programming

Ferroelectric field effect transistors, pluralities of ferroelectric field effect transistors arrayed in row lines and column lines, and methods of forming a plurality of ferroelectric field effect transistors

Ferroelectric field effect transistors, pluralities of ferroelectric field effect transistors arrayed in row lines and column lines, and methods of forming a plurality of ferroelectric field effect transistors

Pitch multiplication spacers and methods of forming the same

Band-engineered multi-gated non-volatile memory device with enhanced attributes

Methods of forming materials between conductive electrical components, and insulating materials

Method and apparatus for a flash memory device comprising a source local interconnect

Double-doped polysilicon floating gate

Formation of silicided contact by ion implantation

Method to form a corrugated structure for enhanced capacitance

Method of forming flash memory

Plug-based floating gate memory

Method for forming a semiconductor buried contact with a removable spacer

Process for enhancing refresh in dynamic random access memory device

Method of forming a memory device and semiconductor device

Expanded implantation of contact holes

Method of forming FLASH memory, method of forming FLASH memory and SRAM circuitry, and etching methods

Cross-point memory compensation

Memory cells

Memory cells

Cross-point memory compensation

Memory cells

Transistors, memory cells and semiconductor constructions

Double-doped polysilicon floating gate

Non-volatile memory cell device and methods

NROM memory cell, memory array, related devices and methods

Forming multi-layer memory arrays

Etch process for aligning a capacitor structure and an adjacent contact corridor

Transistors, memory cells and semiconductor constructions

Constructions comprising insulative materials

Lateral bipolar transistor

MICRON SEMICONDUCTOR INC

Low resistance device element and interconnection structure

BHATTACHARYYA ARUP

Memory cells configured to allow for erasure by enhanced F-N tunneling of holes from a control gate to a charge trapping material

SANDHU GURTEJ S

Pitch multiplication spacers and methods of forming the same

LIU ZENGTAO T

Cross-point memory compensation

PRALL KIRK D

NROM memory cell, memory array, related devices and methods