Plug-based floating gate memory

Abstract

A device and a method of forming a floating gate memory transistor of very small area, thereby allowing a high-density integrated circuit chip, more specifically for Erasable Programmable Read-Only Memory (EPROM) or similar non-volatile devices. In a first embodiment, a method is disclosed that fabricates a programmable memory cell described as a "diffusion cut" cell where a plug-type floating gate contact hole cuts through a diffusion region and partially into a substrate region. In a second embodiment, a method is disclosed that fabricates a programmable memory cell described as an "oxide cut" cell, where the plug-type floating gate contact hole only penetrates a silicon oxide layer. This "oxide cut" cell is formed in a similar fashion except penetration does not go into the diffusion region or substrate.

What is claimed is: 
     
       1. A method of fabricating a minimum area floating gate memory cell within an IC chip contact well comprising the steps of: a. growing and patterning a field oxide on a substrate by a LOCOS process;   b. implanting an impurity element in the substrate to form a diffusion region adjacent the field oxide;   c. depositing an oxide layer over the diffusion region and field oxide;   d. patterning and etching a contact well in the oxide layer, field oxide, diffusion region, and substrate further comprising: i. performing a cell plug masking;   ii. etching the oxide layer;     iii. etching the . .silicon and.!. diffusion region, thereby forming an extended channel;   e. growing a gate/tunnel oxide layer within the contact well;   f. depositing and doping a first polysilicon layer . .with.!. .Iadd.within .Iaddend.the contact well, thereby forming a floating gate and capacitor C1;   g. etching the first polysilicon layer until the only polysilicon is within the contact well forming a polysilicon plug;   h. depositing a second polysilicon layer within the contact well;   i. etching back the second polysilicon layer leaving a thin layer of the second polysilicon on a perimeter of the contact well;   j. depositing an ONO dielectric layer over the second polysilicon layer wherein the ONO dielectric layer is about 100 Å thick;   k. depositing and doping a third polysilicon layer over the contact hole, thereby forming a second capacitor C2 between the third polysilicon layer and the second polysilicon layer wherein a capacitance ratio of C2/C1 is maximized by controlling a depth of the oxide layer of step c, thereby providing a maximum voltage and charge on the floating gate during electrical programming;   l. depositing a tungsten silicide layer over the third polysilicon layer; and then   m. masking and etching the third polysilicon layer and tungsten silicide to form a word line.   
     
     
       2. A method of fabricating a minimum area floating gate memory cell within an IC chip contact well comprising the steps of: a. growing and patterning a field oxide on a substrate by a LOCOS process;   b. implanting an impurity element in the substrate to form a diffusion region adjacent the field oxide;   c. depositing an oxide layer over the diffusion region and field oxide;   d. patterning and etching a contact well in the oxide layer further comprising: i. performing a cell plug masking;   ii. etching the oxide layer;   iii. etching the . .silicon and.!. diffusion region, thereby forming an extended channel;     e. growing a gate/tunnel oxide layer within the contact well, thereby forming a floating gate and a capacitor C1 between the first polysilicon layer and the substrate, said capacitor C1 having a minimal capacitance;   f. depositing and doping a first polysilicon layer within the contact well, thereby forming a floating gate and capacitor C1;   g. etching the first polysilicon layer until the only polysilicon is within the contact well forming a polysilicon plug;   h. depositing a second polysilicon layer within the contact well;   i. etching back the second polysilicon layer leaving a thin layer of the second polysilicon on a perimeter of the contact well;   j. depositing an ONO dielectric layer over the second polysilicon layer wherein the ONO dielectric layer is about 100 Å thick;   k. depositing and doping a third polysilicon layer over the contact hole, thereby forming a second capacitor C2 between the third polysilicon layer and the second polysilicon layer C2 having a larger capacitance than C1;   l. depositing a tungsten silicide layer over the third polysilicon layer; and then   m. masking and etching the third polysilicon layer and tungsten silicide to form a control gate and word line. .Iadd.3. A method of fabricating a floating gate memory cell comprising the steps of:   a. forming a doped region on a substrate;   b. disposing a first layer of dielectric material over said doped region, said first layer of dielectric material having a thickness;   c. forming a contact well extending through said first layer of dielectric material and through said doped region, said contact well having inner walls and a bottom portion;   d. disposing a second layer of dielectric material within said contact well over said inner walls and bottom portion;   e. disposing conductive material within said contact well over said second layer of dielectric material, thereby forming a floating gate and a first capacitor;   f. disposing a third layer of dielectric material within said contact well over said conductive material; and   g. disposing conductive material over said third layer of dielectric material within said contact well, thereby forming a second capacitor, wherein a capacitance ratio between said first capacitor and said second capacitor is maximized by controlling said thickness of said first layer of dielectric material, thereby providing a maximum voltage and charge on said floating gate during electrical programming. .Iaddend..Iadd.4. The method, as set forth in claim 3, further comprising the step of:   (h) forming a conductive line coupled to said conductive material disposed in step (g). .Iaddend..Iadd.5. The method, as set forth in claim 3, wherein step (a) comprises the steps of:   (a1) disposing a field oxide on said substrate, said field oxide having a window therein; and   (a2) implanting an impurity in said substrate through said window.   
     
     
        .Iaddend..Iadd.6.  The method, as set forth in claim 5, wherein step (b) comprises the step of: (b1) disposing an oxide layer over said doped region and over said field oxide. .Iaddend..Iadd.7. The method, as set forth in claim 3, wherein step (e) comprises the steps of:   (e1) disposing a first layer of conductive material within said contact well;   (e2) removing a portion of said first layer of conductive material to leave a plug of conductive material disposed in said bottom portion of said contact well;   (e3) disposing a second layer of conductive material within said contact well; and   (e4) removing a portion of said second layer of conductive material to leave a layer of conductive material disposed on said inner walls of said contact well. .Iaddend..Iadd.8. The method, as set forth in claim 3, wherein step (f) comprises the step of:   (f1) disposing a layer of ONO dielectric approximately 100 angstroms thick within said contact well over said conductive material. .Iaddend..Iadd.9. The method, as set forth in claim 3, wherein said conductive material disposed in steps (e) and (g) is polysilicon. .Iaddend..Iadd.10. The method, as set forth in claim 4, wherein step (h) comprises the steps of:   (h1) depositing a tungsten silicide layer over said conductive material disposed in step (g); and   (h2) masking and etching said conductive material disposed in step (g) and   
     
     
        said tungsten silicide layer to form a word line. .Iaddend..Iadd.11.  A method of fabricating a floating gate memory cell comprising the steps of: a. forming a doped region on a substrate;   b. disposing a first layer of dielectric material over said doped region, said first layer of dielectric material having a thickness;   c. forming a contact well extending through said first layer of dielectric material to said doped region without etching into said doped region, said contact well having inner walls and a bottom portion;   d. disposing a second layer of dielectric material within said contact well over said inner walls and bottom portion;   e. disposing conductive material within said contact well over said second layer of dielectric material, thereby forming a floating gate and a first capacitor;   f. disposing a third layer of dielectric material within said contact well over said conductive material; and   g. disposing conductive material over said third layer of dielectric material within said contact well, thereby forming a second capacitor. .Iaddend..Iadd.12. The method, as set forth in claim 11, further comprising the step of:   (h) forming a conductive line coupled to said conductive material disposed in step (g). .Iaddend..Iadd.13. The method, as set forth in claim 11, wherein step (a) comprises the steps of:   (a1) disposing a field oxide on said substrate, said field oxide having a window therein; and   (a2) implanting an impurity in said substrate through said window.   
     
     
        .Iaddend..Iadd.14.  The method, as set forth in claim 13, wherein step (b) comprises the step of: (b1) disposing an oxide layer over said doped region and over said field oxide. .Iaddend..Iadd.15. The method, as set forth in claim 11, wherein step (e) comprises the steps of:   (e1) disposing a first layer of conductive material within said contact well;   (e2) removing a portion of said first layer of conductive material to leave a plug of conductive material disposed in said bottom portion of said contact well;   (e3) disposing a second layer of conductive material within said contact well; and   (e4) removing a portion of said second layer of conductive material to leave a layer of conductive material disposed on said inner walls of said contact well. .Iaddend..Iadd.16. The method, as set forth in claim 11, wherein step (f) comprises the step of:   (f1) disposing a layer of ONO dielectric approximately 100 angstroms thick within said contact well over said conductive material. .Iaddend..Iadd.17. The method, as set forth in claim 11, wherein said conductive material disposed in steps (e) and (g) is polysilicon. .Iaddend..Iadd.18. The method, as set forth in claim 12, wherein step (h) comprises the steps of:   (h1) depositing a tungsten silicide layer over said conductive material disposed in step (g); and   (h2) masking and etching said conductive material disposed in step (g) and   
     
     
        said tungsten silicide layer to form a word line. .Iaddend..Iadd.19.  The method, as set forth in claim 12, wherein a capacitance ratio between said first capacitor and said second capacitor is maximized by controlling said thickness of said first layer of dielectric material, thereby providing a maximum voltage and charge on said floating gate during electrical programming. .Iaddend.