Inventor

BASU ANIRBAN

US70 patents

⚠️ This page may combine multiple inventors who share the name “BASU ANIRBAN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

BASU ANIRBAN

IBM

Vertical field effect transistors with controlled overlap between gate electrode and source/drain contacts

III-V nanowire FET with compositionally-graded channel and wide-bandgap core

III-V finFETs on silicon substrate

Reducing direct source-to-drain tunneling in field effect transistors with low effective mass channels

Vertical field effect transistors with controlled overlap between gate electrode and source/drain contacts

Reducing direct source-to-drain tunneling in field effect transistors with low effective mass channels

Reducing direct source-to-drain tunneling in field effect transistors with low effective mass channels

Remote object sensing in video

Nanowire field effect transistor with inner and outer gates

Fabrication process for mitigating external resistance and interface state density in a multigate device

Low interfacial defect field effect transistor

Elemental semiconductor material contact for high electron mobility transistor

Charge carrier transport facilitated by strain

Device isolation using preferential oxidation of the bulk substrate

Device isolation using preferential oxidation of the bulk substrate

Device isolation using preferential oxidation of the bulk substrate

Fabrication of III-V-on-insulator platforms for semiconductor devices

Fabrication process for mitigating external resistance of a multigate device

Charge carrier transport facilitated by strain

Fabrication process for mitigating external resistance of a multigate device

Silicon-containing, tunneling field-effect transistor including III-N source

Nanowire field effect transistor with inner and outer gates

Vertical compound semiconductor field effect transistor on a group IV semiconductor substrate

System and method for minimizing the time to park a vehicle

Device isolation using preferential oxidation of the bulk substrate

Charge carrier transport facilitated by strain

Silicon-containing, tunneling field-effect transistor including III-N source

Multi-junction solar cell

Device isolation for III-V substrates

III-V semiconductor device having self-aligned contacts

Electricity-less water disinfection

Multi-junction solar cell

Device isolation using preferential oxidation of the bulk substrate

Device isolation for III-V substrates

Multi-junction solar cell

Silicon-containing, tunneling field-effect transistor including III-N source

Device isolation for III-V substrates

Fabrication process for mitigating external resistance of a multigate device

III-V MOSFET with strained channel and semi-insulating bottom barrier

Device isolation for III-V substrates

Fabrication of III-V-on-insulator platforms for semiconductor devices

Fin field effect transistor including self-aligned raised active regions

III-V nanowire FET with compositionally-graded channel and wide-bandgap core

GLOBALFOUNDRIES INC

Contact metallurgy for self-aligned high electron mobility transistor

III-V semiconductor device having self-aligned contacts

Suspended body field effect transistor

MICROSOFT TECHNOLOGY LICENSING LLC

Instant enforcement of centrally configured IT policies

Using IP heuristics to protect access tokens from theft and replay

ADOBE INC

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