Fin field effect transistor including self-aligned raised active regions

Abstract

Fin mask structures are formed over a semiconductor material portion on a crystalline insulator layer. A disposable gate structure and a gate spacer are formed over the fin mask structures. Employing the disposable gate structure and the gate spacer as an etch mask, physically exposed portions of the fin mask structures and the semiconductor material portion are removed by an etch. A source region and a drain region are formed by selective epitaxy of a semiconductor material from physically exposed surfaces of the crystalline insulator layer. The disposable gate structure is removed selective to the source region and the drain region. Semiconductor fins are formed by anisotropically etching portions of the semiconductor material portion, employing the gate spacer and the fin mask structures as etch masks. A gate dielectric and a gate electrode are formed within the gate cavity.

What is claimed is: 
     
       1. A method of forming a semiconductor structure comprising:
 forming at least one fin-defining mask structure over a semiconductor material portion on an insulator layer; 
 forming a disposable gate structure and a gate spacer over said at least one fin-defining mask structure; 
 etching physically exposed portions of said at least one fin-defining mask structure and said semiconductor material portion employing said disposable gate structure and said gate spacer as an etch mask; 
 removing said disposable gate structure selective to said gate spacer; and 
 forming at least one semiconductor fin by etching said semiconductor material portion employing said gate spacer and said at least one fin-defining mask structure as an etch mask. 
 
     
     
       2. The method of  claim 1 , further comprising growing a source region and a drain region from physically exposed surfaces of said insulator layer after said etching of said physically exposed portions of said at least one fin-defining mask structure and said semiconductor material portion. 
     
     
       3. The method of  claim 2 , wherein said source region and said drain region comprise a doped single crystalline semiconductor material that is epitaxially aligned to said insulator layer. 
     
     
       4. The method of  claim 2 , further comprising forming a gate stack including a gate dielectric and a gate electrode over said at least one semiconductor fin. 
     
     
       5. The method of  claim 1 , wherein remaining portions of said semiconductor material portion after formation of said at least one semiconductor fin comprise a first end portion and a second end portion, wherein each of said first end portion and said second end portion has a same width as said gate spacer. 
     
     
       6. The method of  claim 5 , further comprising:
 depositing a semiconductor material directly on physically exposed surfaces of said insulator layer; and 
 removing portions of said deposited semiconductor material by planarization, wherein remaining portions of said deposited semiconductor material constitutes a source region and a drain region. 
 
     
     
       7. The method of  claim 6 , wherein a sidewall of said source region is vertically coincident with a sidewall of said semiconductor material portion, and a sidewall of said drain region is vertically coincident with another sidewall of said semiconductor material portion. 
     
     
       8. The method of  claim 5 , wherein said insulator layer is single crystalline, and said deposited semiconductor material is single crystalline. 
     
     
       9. The method of  claim 5 , wherein portions of a top surface of said insulator layer is physically exposed after formation of said at least one semiconductor fin. 
     
     
       10. The method of  claim 1 , further comprising:
 removing said at least one fin-defining mask structure selective to said at least one semiconductor fin; and 
 forming another gate spacer directly on portions of sidewall surfaces of said source region and said drain region. 
 
     
     
       11. The method of  claim 1 , wherein said forming said at least one fin-defining mask structure comprises:
 forming a planar dielectric material layer; and 
 lithographically patterning said planar dielectric material layer. 
 
     
     
       12. The method of  claim 1 , wherein said forming said disposable gate structure comprises:
 depositing a disposable gate material layer; and 
 patterning said disposable gate material layer. 
 
     
     
       13. The method of  claim 1 , wherein said gate spacer is formed by providing a spacer dielectric material that is different from a dielectric material that provides said at least one fin-defining mask structure and anisotropically etching said spacer dielectric material. 
     
     
       14. The method of  claim 1 , wherein etching physically exposed portions of said at least one fin-defining mask structure and said semiconductor material portion comprises an anisotropic etch. 
     
     
       15. The method of  claim 1 , wherein said removing said disposable gate structure selective to said gate spacer provides a gate cavity within a volume previously occupied by said disposable gate structure. 
     
     
       16. The method of  claim 15 , further comprising filling said gate cavity with a replacement gate structure.