Inventor

WE HONG BOK

US83 patents

Patents

50 patents

US9443824B1Sep 13, 2016

Cavity bridge connection for die split architecture

QUALCOMM INC102 citations98

US9368450B1Jun 14, 2016

Integrated device package comprising bridge in litho-etchable layer

QUALCOMM INC119 citations98

US10410971B2Sep 10, 2019

Thermal and electromagnetic interference shielding for die embedded in package substrate

QUALCOMM INC37 citations93

US9633977B1Apr 25, 2017

Integrated device comprising flexible connector between integrated circuit (IC) packages

QUALCOMM INC32 citations93

US9679855B1Jun 13, 2017

Polymer crack stop seal ring structure in wafer level package

QUALCOMM INC20 citations90

US11682607B2Jun 20, 2023

Package having a substrate comprising surface interconnects aligned with a surface of the substrate

QUALCOMM INC8 citations84

US9642259B2May 2, 2017

Package comprising a substrate with interconnect routing over solder resist layer and an integrated device coupled to the substrate and method for manufacturing the package

QUALCOMM INC2 citations73

US10181410B2Jan 15, 2019

Integrated circuit package comprising surface capacitor and ground plane

QUALCOMM INC3 citations73

US10157823B2Dec 18, 2018

High density fan out package structure

QUALCOMM INC6 citations73

US9799628B2Oct 24, 2017

Stacked package configurations and methods of making the same

QUALCOMM INC2 citations73

US9659850B2May 23, 2017

Package substrate comprising capacitor, redistribution layer and discrete coaxial connection

QUALCOMM INC4 citations73

US9633950B1Apr 25, 2017

Integrated device comprising flexible connector between integrated circuit (IC) packages

QUALCOMM INC5 citations73

US9628052B2Apr 18, 2017

Embedded multi-terminal capacitor

QUALCOMM INC2 citations73

US9613942B2Apr 4, 2017

Interposer for a package-on-package structure

QUALCOMM INC5 citations73

US9596768B2Mar 14, 2017

Substrate with conductive vias

QUALCOMM INC6 citations73

US9595494B2Mar 14, 2017

Semiconductor package with high density die to die connection and method of making the same

QUALCOMM INC3 citations73

US9502490B2Nov 22, 2016

Embedded package substrate capacitor

QUALCOMM INC4 citations73

US9355963B2May 31, 2016

Semiconductor package interconnections and method of making the same

QUALCOMM INC4 citations73

US9230936B2Jan 5, 2016

Integrated device comprising high density interconnects and redistribution layers

QUALCOMM INC4 citations73

US11183446B1Nov 23, 2021

X.5 layer substrate

QUALCOMM INC4 citations72

US10403707B2Sep 3, 2019

Array type inductor

QUALCOMM INC2 citations72

US9385077B2Jul 5, 2016

Integrated device comprising coaxial interconnect

QUALCOMM INC2 citations63

US12543599B2Feb 3, 2026

Package comprising a first substrate, a second substrate and an electrical device coupled to a bottom surface of the second substrate

QUALCOMM INC1 citations62

US12381174B2Aug 5, 2025

Integrated circuit (IC) packages employing wire bond channel over package substrate, and related fabrication methods

QUALCOMM INC0 citations62

US11955409B2Apr 9, 2024

Substrate comprising interconnects in a core layer configured for skew matching

QUALCOMM INC0 citations62

US11832391B2Nov 28, 2023

Terminal connection routing and method the same

QUALCOMM INC0 citations62

US11817365B2Nov 14, 2023

Thermal mitigation die using back side etch

QUALCOMM INC0 citations62

US11804645B2Oct 31, 2023

Multi-sided antenna module employing antennas on multiple sides of a package substrate for enhanced antenna coverage, and related fabrication methods

QUALCOMM INC0 citations62

US11776888B2Oct 3, 2023

Package with a substrate comprising protruding pad interconnects

QUALCOMM INC0 citations62

US11749611B2Sep 5, 2023

Package with a substrate comprising periphery interconnects

QUALCOMM INC0 citations62

US11715688B2Aug 1, 2023

Variable dielectric constant materials in same layer of a package

QUALCOMM INC0 citations62

US11594491B2Feb 28, 2023

Multi-die interconnect

QUALCOMM INC1 citations62

US11581251B2Feb 14, 2023

Package comprising inter-substrate gradient interconnect structure

QUALCOMM INC0 citations62

US11545425B2Jan 3, 2023

Substrate comprising interconnects embedded in a solder resist layer

QUALCOMM INC1 citations62

US11296022B2Apr 5, 2022

Package and substrate comprising interconnects with semi-circular planar shape and/or trapezoid planar shape

QUALCOMM INC0 citations62

US11296024B2Apr 5, 2022

Nested interconnect structure in concentric arrangement for improved package architecture

QUALCOMM INC0 citations62

US11289453B2Mar 29, 2022

Package comprising a substrate and a high-density interconnect structure coupled to the substrate

QUALCOMM INC1 citations62

US11258165B2Feb 22, 2022

Asymmetric antenna structure

QUALCOMM INC0 citations62

US11101220B2Aug 24, 2021

Through-package partial via on package edge

QUALCOMM INC0 citations62

US11075260B2Jul 27, 2021

Substrate comprising recessed interconnects and a surface mounted passive component

QUALCOMM INC0 citations62

US11043740B2Jun 22, 2021

Enhanced antenna module with shield layer

QUALCOMM INC0 citations62

US11791320B2Oct 17, 2023

Integrated circuit (IC) packages employing a package substrate with a double side embedded trace substrate (ETS), and related fabrication methods

QUALCOMM INC0 citations61

US12581966B2Mar 17, 2026

Electronic component placed on core of substrate

QUALCOMM INC0 citations60

US12500146B2Dec 16, 2025

Substrate(s) for an integrated circuit (IC) package employing a metal core for improved electrical shielding and structural strength, and related IC packages and fabrication methods

QUALCOMM INC0 citations60

US12243855B2Mar 4, 2025

Package comprising channel interconnects located between solder interconnects

QUALCOMM INC0 citations60

US11177223B1Nov 16, 2021

Electromagnetic interference shielding for packages and modules

QUALCOMM INC0 citations60

Showing the top 50 of 83 patents by PatentIndex Score.

WE HONG BOK

Patents

Cavity bridge connection for die split architecture

Integrated device package comprising bridge in litho-etchable layer

Thermal and electromagnetic interference shielding for die embedded in package substrate

Integrated device comprising flexible connector between integrated circuit (IC) packages

Polymer crack stop seal ring structure in wafer level package

Package having a substrate comprising surface interconnects aligned with a surface of the substrate

Embedded bridge structure in a substrate

Integrated device package comprising silicon bridge in an encapsulation layer

Damascene re-distribution layer (RDL) in fan out split die application

Package-on-package (POP) structure including multiple dies

Package comprising a substrate with interconnect routing over solder resist layer and an integrated device coupled to the substrate and method for manufacturing the package

Integrated circuit package comprising surface capacitor and ground plane

High density fan out package structure

Stacked package configurations and methods of making the same

Package substrate comprising capacitor, redistribution layer and discrete coaxial connection

Integrated device comprising flexible connector between integrated circuit (IC) packages

Embedded multi-terminal capacitor

Interposer for a package-on-package structure

Substrate with conductive vias

Semiconductor package with high density die to die connection and method of making the same

Embedded package substrate capacitor

Semiconductor package interconnections and method of making the same

Integrated device comprising high density interconnects and redistribution layers

X.5 layer substrate

Array type inductor

Integrated device comprising coaxial interconnect

Package comprising a first substrate, a second substrate and an electrical device coupled to a bottom surface of the second substrate

Integrated circuit (IC) packages employing wire bond channel over package substrate, and related fabrication methods

Substrate comprising interconnects in a core layer configured for skew matching

Terminal connection routing and method the same

Thermal mitigation die using back side etch

Multi-sided antenna module employing antennas on multiple sides of a package substrate for enhanced antenna coverage, and related fabrication methods

Package with a substrate comprising protruding pad interconnects

Package with a substrate comprising periphery interconnects

Variable dielectric constant materials in same layer of a package

Multi-die interconnect

Package comprising inter-substrate gradient interconnect structure

Substrate comprising interconnects embedded in a solder resist layer

Package and substrate comprising interconnects with semi-circular planar shape and/or trapezoid planar shape

Nested interconnect structure in concentric arrangement for improved package architecture

Package comprising a substrate and a high-density interconnect structure coupled to the substrate

Asymmetric antenna structure

Through-package partial via on package edge

Substrate comprising recessed interconnects and a surface mounted passive component

Enhanced antenna module with shield layer

Integrated circuit (IC) packages employing a package substrate with a double side embedded trace substrate (ETS), and related fabrication methods

Electronic component placed on core of substrate

Substrate(s) for an integrated circuit (IC) package employing a metal core for improved electrical shielding and structural strength, and related IC packages and fabrication methods

Package comprising channel interconnects located between solder interconnects

Electromagnetic interference shielding for packages and modules