P
US11296024B2ActiveUtilityPatentIndex 62

Nested interconnect structure in concentric arrangement for improved package architecture

Assignee: QUALCOMM INCPriority: May 15, 2020Filed: May 15, 2020Granted: Apr 5, 2022
Est. expiryMay 15, 2040(~13.9 yrs left)· nominal 20-yr term from priority
Inventors:PATIL ANIKETWE HONG BOKKIM JONGHAE
H10W 74/142H10W 72/9413H10W 44/223H10W 70/09H10W 70/60H10W 90/724H10W 90/722H10W 72/247H10W 72/07254H10W 70/6528H10W 72/241H10W 74/117H10W 74/01H10W 70/685H10W 70/05H10W 74/019H10W 74/014H10P 72/74H10P 72/7424H10W 20/43H10W 90/701H01L 23/528H01L 21/56H01L 23/3128H01L 21/4857H01L 23/49822
62
PatentIndex Score
0
Cited by
21
References
17
Claims

Abstract

An integrated circuit (IC) package is described. The IC package includes back-end-of-line layers on a substrate. The IC package also includes a nested interconnect structure on the back-end-of-line layers on the substrate. The nested interconnect structure is composed of an inner core pad and an outer ring pad in a concentric arrangement. The IC package further includes a redistribution layer on the nested interconnect structure. The IC package also includes an under bump metallization layer on the redistribution layer to support package balls.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
       1. An integrated circuit (IC) package, comprising:
 back-end-of-line layers on a substrate; 
 a nested interconnect structure on the back-end-of-line layers on the substrate, in which the nested interconnect structure comprises an inner core pad and an outer ring pad in a concentric arrangement, and in which the inner core pad supports a first network of the IC package and the outer ring pad supports a second network of the IC package; 
 a redistribution layer on the nested interconnect structure; and 
 an under bump metallization layer on the redistribution layer to support package balls. 
 
     
     
       2. The IC package of  claim 1 , in which the first network of the IC package comprises a power network and the second network of the IC package comprises a ground network. 
     
     
       3. The IC package of  claim 1 , in which the first network of the IC package comprises a signal network and the second network of the IC package comprises a ground network. 
     
     
       4. The IC package of  claim 1 , in which the first network of the IC package comprises a first differential signal and the second network of the IC package comprises a second differential signal. 
     
     
       5. The IC package of  claim 1 , in which the nested interconnect structure comprises a nested aluminum pad (AP) layer structure comprising a central AP pad and an outer ring AP pad. 
     
     
       6. The IC package of  claim 1 , in which the substrate comprises an active die. 
     
     
       7. The IC package of  claim 6 , in which the active die comprises a server die. 
     
     
       8. The IC package of  claim 6 , in which the active die comprises a radio frequency (RF) die. 
     
     
       9. The IC package of  claim 1 , further comprising:
 a mold compound on a surface of the redistribution layer and sidewalls of the nested interconnect structure, the back-end-of-line layers, and the substrate. 
 
     
     
       10. A method for fabricating a nested interconnect structure in a concentric arrangement, comprising:
 forming an inner core pad and an outer ring pad in the concentric arrangement to contact back-end-of-line layers on a substrate as the nested interconnect structure; 
 forming redistribution layers on the nested interconnect structure to separately contact the inner core pad and the outer ring pad; 
 forming an under bump metallization layer on the redistribution layers to support package balls; 
 depositing a mold compound on a surface of the substrate, a bonding film, and sidewalls of the nested interconnect structure and the back-end-of-line layers; and 
 back-grinding the mold compound until the surface of the substrate is exposed. 
 
     
     
       11. The method of  claim 10 , further comprising:
 supporting, by the inner core pad, a first network of the IC package; and 
 supporting, by the outer ring pad, a second network of the IC package. 
 
     
     
       12. The method of  claim 11 , in which the first network of the IC package comprises a power network and the second network of the IC package comprises a ground network. 
     
     
       13. The method of  claim 11 , in which the first network of the IC package comprises a signal network and the second network of the IC package comprises a ground network. 
     
     
       14. The method of  claim 11 , in which the first network of the IC package comprises a first differential signal and the second network of the IC package comprises a second differential signal. 
     
     
       15. An integrated circuit (IC) package, comprising:
 back-end-of-line layers on a substrate; 
 a nested interconnect structure on the back-end-of-line layers on the substrate, in which the nested interconnect structure comprises an inner core pad and an outer ring pad in a concentric arrangement, and in which the inner core pad supports a first network of the IC package and the outer ring pad supports a second network of the IC package; 
 a redistribution layer on the nested interconnect structure; and 
 means for supporting package balls on the redistribution layer. 
 
     
     
       16. The IC package of  claim 15 , in which the first network of the IC package comprises a power network and the second network of the IC package comprises a ground network. 
     
     
       17. The IC package of  claim 15 , in which the first network of the IC package comprises a first differential signal and the second network of the IC package comprises a second differential signal.

Cited by (0)

No later patents cite this yet.

References (0)

No backward citations on record.