Inventor

PATIL ANIKET

US52 patents

⚠️ This page may combine multiple inventors who share the name “PATIL ANIKET”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

PATIL ANIKET

QUALCOMM INC

Package having a substrate comprising surface interconnects aligned with a surface of the substrate

Package comprising a substrate with interconnect routing over solder resist layer and an integrated device coupled to the substrate and method for manufacturing the package

Package comprising optical integrated device

Package comprising a first substrate, a second substrate and an electrical device coupled to a bottom surface of the second substrate

Integrated circuit (IC) packages employing wire bond channel over package substrate, and related fabrication methods

Substrate comprising interconnects in a core layer configured for skew matching

Terminal connection routing and method the same

Thermal mitigation die using back side etch

Multi-sided antenna module employing antennas on multiple sides of a package substrate for enhanced antenna coverage, and related fabrication methods

Integrated circuit (IC) with reconstituted die interposer for improved connectivity, and related methods of fabrication

Package with a substrate comprising periphery interconnects

Variable dielectric constant materials in same layer of a package

Uniform via pad structure having covered traces between partially covered pads

Package comprising inter-substrate gradient interconnect structure

Nested interconnect structure in concentric arrangement for improved package architecture

Package and substrate comprising interconnects with semi-circular planar shape and/or trapezoid planar shape

Package comprising a substrate and a high-density interconnect structure coupled to the substrate

Through-package partial via on package edge

Ground shield plane for ball grid array (BGA) package

Integrated circuit (IC) packages employing a package substrate with a double side embedded trace substrate (ETS), and related fabrication methods

Package comprising channel interconnects located between solder interconnects

Electromagnetic interference shielding for packages and modules

Thermal structures adapted to electronic device heights in integrated circuit (IC) packages

Package comprising a die and die side redistribution layers (RDL)

Substrate with multiple core layers to provide varied thickness cavities supporting varied thickness embedded electrical devices, and related integrated circuit (IC) packages and fabrication methods

Circular bond finger pad

Packages with local high-density routing region embedded within an insulating layer

Package comprising a substrate and interconnect device configured for diagonal routing

Substrate comprising a high-density interconnect portion embedded in a core layer

Package comprising an integrated device coupled to a substrate through a cavity

Multi-terminal integrated passive devices embedded on die and a method for fabricating the multi-terminal integrated passive devices

Passive device orientation in core for improved power delivery in package

Split conductive pad for device terminal

Recess structure for padless stack via

Integrated circuit (IC) package employing added metal for embedded metal traces in ETS-based substrate for reduced signal path impedance, and related fabrication methods

Package comprising passive component between substrates for improved power distribution network (PDN) performance

Antenna module

Package comprising multi-level vertically stacked redistribution portions

Ultra-low profile stacked RDL semiconductor package

Hybrid package apparatus and method of fabricating

Redistribution layer connection

Integrated circuit (IC) packages employing split, double-sided metallization structures to facilitate a semiconductor die (“die”) module employing stacked dice, and related fabrication methods

Integrated circuit (IC) packages employing a thermal conductive package substrate with die region split, and related fabrication methods

Substrate(s) for an integrated circuit (IC) package employing a core layer and an adjacent insulation layer(s) with an embedded metal structure(s) positioned from the core layer

ASM IP HOLDING BV

Susceptor shaft

Susceptor support

Susceptor shaft

Susceptor shaft

REXER PETER

Security enhancement through application access control

EATON INTELLIGENT POWER LTD

Integrated direct mount branch protection for variable frequency drive