Inventor

NING GUOXIANG

US42 patents

⚠️ This page may combine multiple inventors who share the name “NING GUOXIANG”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

NING GUOXIANG

GLOBALFOUNDRIES INC

Self-aligned metal wire on contact structure and method for forming same

FinFET cut isolation opening revision to compensate for overlay inaccuracy

Interconnects separated by a dielectric region formed using removable sacrificial plugs

Circuit structures and methods of fabrication with enhanced contact via electrical connection

Geometry vectorization for mask process correction

FinFET cut isolation opening revision to compensate for overlay inaccuracy

Anti-fuse for an integrated circuit (IC) product and method of making such an anti-fuse for an IC product

Gap fill void and connection structures

Anti-fuse with self aligned via patterning

Achieving a critical dimension target based on resist characteristics

Controlling back-end-of-line dimensions of semiconductor devices

Device/health of line (HOL) aware eBeam based overlay (EBO OVL) structure

Interconnects with non-mandrel cuts formed by early block patterning

Chamferless interconnect vias of semiconductor devices

Method for selective re-routing of selected areas in a target layer and in adjacent interconnecting layers of an IC device

Method for selective re-routing of selected areas in a target layer and in adjacent interconnecting layers of an IC device

Alternating space decomposition in circuit structure fabrication

Customized alleviation of stresses generated by through-substrate via(S)

Self-aligned quadruple patterning pitch walking solution

Dummy assist features for pattern support

Overlay mark dependent dummy fill to mitigate gate height variation

Overlay mark dependent dummy fill to mitigate gate height variation

Metrology pattern layout and method of use thereof

Method wherein test cells and dummy cells are included into a layout of an integrated circuit

Method wherein test cells and dummy cells are included into a layout of an integrated circuit

Reticle, system comprising a plurality of reticles and method for the formation thereof

Metrology pattern layout and method of use thereof

Efficient optical proximity correction repair flow method and apparatus

Overlay structures

Semiconductor device resolution enhancement by etching multiple sides of a mask

Semiconductor device resolution enhancement by etching multiple sides of a mask

Forming alignment mark and resulting mark

Overlay mark structures

Double pass diluted ultraviolet reticle inspection

Multiple threshold convergent OPC model

Mask error compensation by optical modeling calibration

GLOBALFOUNDRIES US INC

Fin-based anti-fuse device for integrated circuit (IC) products, methods of making such an anti-fuse device and IC products comprising such an anti-fuse device

SRAM bit cells formed with dummy structures

Gap fill void and connection structures

GLOBALFOUNDRIES SG PTE LTD

Pattern classification based proximity corrections for reticle fabrication

Monitoring pattern for devices

CHARTERED SEMICONDUCTOR MFG

Cross technology reticles