Inventor

BARASKAR ASHISH

US33 patents

⚠️ This page may combine multiple inventors who share the name “BARASKAR ASHISH”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

BARASKAR ASHISH

SANDISK TECHNOLOGIES LLC

Memory hole size variation in a 3D stacked memory

Three-dimensional memory device containing structurally reinforced pedestal channel portions and method of making thereof

Forming memory cell film in stack opening

Three-dimensional memory device with select transistor having charge trapping gate dielectric layer and methods of making and operating thereof

Three-dimensional memory device including a silicon-germanium source contact layer and method of making the same

Three-dimensional memory device containing plural work function word lines and methods of forming the same

Memory device with compensation for erase speed variations due to blocking oxide layer thinning

Multi-pass programming process for memory device which omits verify test in first program pass

Three-dimensional memory devices using carbon-doped aluminum oxide backside blocking dielectric layer for etch resistivity enhancement and methods of making the same

Memory device with compensation for erase speed variations due to blocking oxide layer thinning

Memory device with compensation for program speed variations due to block oxide thinning

Method of fabricating 3D NAND

Method of forming memory cell film

Three-dimensional memory device including a silicon-germanium source contact layer and method of making the same

Methods for reusing substrates during manufacture of a bonded assembly including a logic die and a memory die

Three-dimensional memory device containing plural work function word lines and methods of forming the same

Multi-pass programming process for memory device which omits verify test in first program pass

Reprogramming memory cells to tighten threshold voltage distributions and improve data retention

Non-volatile memory with reduced program speed variation

Channel pre-charge to suppress disturb of select gate transistors during erase in memory

Three-dimensional memory device containing III-V compound semiconductor channel and contacts and method of making the same

Three-dimensional memory device containing III-V compound semiconductor channel and contacts and method of making the same

Three-dimensional memory device containing III-V compound semiconductor channel and contacts and method of making the same

Memory device with compensation for program speed variations due to block oxide thinning

Three-dimensional memory device with high mobility channels and nickel aluminum silicide or germanide drain contacts and method of making the same

Three-dimensional memory device with high mobility channels and nickel aluminum silicide or germanide drain contacts and method of making the same

Modified verify scheme for programming a memory apparatus

Memory device with compensation for program speed variations due to block oxide thinning

Reducing charge loss in data memory cell adjacent to dummy memory cell

GLOBALFOUNDRIES INC

Methods of fabricating nanowire structures

Semiconductor fuses with nanowire fuse links and fabrication methods thereof

Semiconductor fuses with nanowire fuse links and fabrication methods thereof

Methods of forming group III-V semiconductor materials on group IV substrates and the resulting substrate structures