Memory hole size variation in a 3D stacked memory

Abstract

Techniques are provided for fabricating a memory device in which the memory cells have a uniform program and erase speed. In one aspect, a memory device is provided with memory holes having diameters which become progressively smaller as a distance between the memory holes and a local interconnect become progressively larger. In another aspect, a fabrication process is provided for such a memory device. The memory holes which are relatively closer to the local interconnect have a relatively thinner blocking oxide layer due to etching used to remove a sacrificial material of the control gate layers. The increased diameter compensates for the thinner blocking oxide layer.

We claim: 
     
       1. An apparatus, comprising:
 a plurality of layers in a stack, the plurality of layers comprising word line layers which are vertically spaced apart from one another by dielectric layers, the plurality of layers are adjacent to a local interconnect of the stack, the local interconnect extends through the stack; and 
 a set of memory holes which extend through the stack, each memory hole of the set of memory holes comprises a sidewall, and along the sidewall, a blocking oxide layer followed by a charge trapping layer, a tunnel oxide layer and a polysilicon channel layer, wherein the memory holes of the set of memory holes have diameters which are progressively smaller as a distance between the memory holes and the local interconnect is progressively larger and widths of the blocking oxide layers are relatively smaller when the distances are relatively smaller. 
 
     
     
       2. The apparatus of  claim 1 , wherein:
 the memory holes are arranged in at least a first row and a second row which are parallel to the local interconnect; 
 a distance between the first row and the local interconnect is less than a distance between the second row and the local interconnect; and 
 a diameter of the memory holes arranged in the first row is larger than a diameter of the memory holes arranged in the second row. 
 
     
     
       3. The apparatus of  claim 1 , wherein:
 the memory holes are arranged in a plurality of rows which are parallel to the local interconnect; 
 in the plurality of rows, memory holes in a row furthest from the local interconnect have a smallest diameter and memory holes in a row closest to the local interconnect have a largest diameter; and 
 the largest diameter is at least 5-10% larger than the smallest diameter. 
 
     
     
       4. The apparatus of  claim 1 , wherein:
 the plurality of layers extend from the local interconnect of the stack to an additional local interconnect of the stack which is parallel to the local interconnect, the additional local interconnect extends through the stack; 
 a first portion of the plurality of layers is adjacent to the local interconnect; 
 a second portion of the plurality of layers is adjacent to the additional local interconnect; 
 the set of memory holes is in the first portion of the plurality of layers; 
 an additional set of memory holes is in the second portion of the plurality of layers; and 
 each memory hole of the additional set of memory holes comprises a sidewall, and along the sidewall, a blocking oxide layer followed by a charge trapping layer, a tunnel oxide layer and a polysilicon channel layer, wherein the memory holes of the additional set of memory holes are at different distances from the additional local interconnect, and each memory hole of the additional set of memory holes has a diameter which is relatively larger when a distance of the memory hole of the additional set of memory holes from the additional local interconnect is relatively smaller. 
 
     
     
       5. The apparatus of  claim 1 , wherein:
 each memory hole of the set of memory holes comprises a lower portion of the memory hole below an upper portion of the memory hole; 
 a diameter of the lower portion of the memory hole is common in the set of memory holes; and 
 the diameters which are progressively smaller as a distance between the memory holes and the local interconnect is progressively larger, comprises a diameter of the upper portion of the memory hole. 
 
     
     
       6. The apparatus of  claim 5 , wherein for each memory hole of the set of memory holes:
 the diameter of the lower portion of the memory hole is a diameter at a top of the lower portion of the memory hole; and 
 the diameter of the upper portion of the memory hole is a diameter at a top of the upper portion of the memory hole. 
 
     
     
       7. The apparatus of  claim 5 , wherein:
 in the upper portion of each memory hole of the set of memory holes, an average width of the blocking oxide layer is relatively smaller when the distance of the memory hole of the set of memory holes from the local interconnect is relatively smaller. 
 
     
     
       8. The apparatus of  claim 7 , wherein:
 for each memory hole of the set of memory holes, an average width of the blocking oxide layer in the lower portion of the memory hole is wider than an average width of the blocking oxide layer in the upper portion of the memory hole. 
 
     
     
       9. The apparatus of  claim 1 , wherein:
 for each memory hole of the set of memory holes, the diameter of the memory hole which is relatively larger when the distance of the memory hole of the set of memory holes from the local interconnect is relatively smaller, comprises a diameter at a top of the memory hole. 
 
     
     
       10. An apparatus, comprising:
 a plurality of control gate layers which are vertically spaced apart from one another by dielectric layers in a stack, the stack comprising a plurality of edges which define a perimeter of the stack; 
 a first row of memory holes which extend through the stack, each memory hole of the first row of memory holes comprises a first diameter at a top of the memory hole; and 
 a second row of memory holes which extend through the stack, each memory hole of the second row of memory holes comprises a second diameter at a top of the memory hole, wherein:
 the first diameter is greater than the second diameter; 
 the first row of memory holes is parallel to an edge of the plurality of edges; 
 the second row of memory holes is parallel to the edge; 
 
 a distance between the first row of memory holes and the edge is less than a distance between the second row of memory holes and the edge;
 each memory hole of the first row of memory holes and each memory hole of the second row of memory holes comprises a sidewall, and along the sidewall, a blocking oxide layer followed by a charge trapping layer, a tunnel oxide layer and a channel layer; and 
 a width of the blocking oxide layer in the first row of memory holes is less than a width of the blocking oxide layer in the second row of memory holes. 
 
 
     
     
       11. The apparatus of  claim 10 , wherein:
 the first diameter is greater than the second diameter by at least 5-10%.