Inventor · disambiguated record
Yingda Dong
Also filed as: DONG YINGDA
243 granted patents·15 pending applications·4,426 citations·filing 2006–2025
99Inventor score
Files withSANDISK TECHNOLOGIES INC114SANDISK TECHNOLOGIES LLC73MICRON TECHNOLOGY INC32SANDISK CORP23DONG YINGDA8
Top patents by PatentIndex Score
258 records- 0199US9812462B1Memory hole size variation in a 3D stacked memorySANDISK TECHNOLOGIES LLC·Filed 2016·Granted Nov 7, 2017·104 cites·11 claims
- 0299US9406693B1Selective removal of charge-trapping layer for select gate transistors and dummy memory cells in 3D stacked memorySANDISK TECHNOLOGIES INC·Filed 2015·Granted Aug 2, 2016·66 cites·22 claims
- 0399US8670285B2Reducing weak-erase type read disturb in 3D non-volatile memoryDONG YINGDA·Filed 2012·Granted Mar 11, 2014·70 cites·20 claims
- 0499US7898864B2Read operation for memory with compensation for coupling based on write-erase cyclesSANDISK CORP·Filed 2009·Granted Mar 1, 2011·451 cites·20 claims
- 0598US9887002B1Dummy word line bias ramp rate during programmingSANDISK TECHNOLOGIES LLC·Filed 2017·Granted Feb 6, 2018·36 cites·20 claims
- 0698US9576971B2Three-dimensional memory structure having a back gate electrodeSANDISK TECHNOLOGIES INC·Filed 2014·Granted Feb 21, 2017·32 cites·9 claims
- 0798US9460805B1Word line dependent channel pre-charge for memorySANDISK TECHNOLOGIES INC·Filed 2015·Granted Oct 4, 2016·52 cites·20 claims
- 0898US9343156B1Balancing programming speeds of memory cells in a 3D stacked memorySANDISK TECHNOLOGIES INC·Filed 2015·Granted May 17, 2016·45 cites·12 claims
- 0998US7468911B2Non-volatile memory using multiple boosting modes for reduced program disturbSANDISK CORP·Filed 2006·Granted Dec 23, 2008·93 cites·18 claims
- 1098US7450421B2Data pattern sensitivity compensation using different voltageSANDISK CORP·Filed 2006·Granted Nov 11, 2008·90 cites·26 claims
- 1198US7310272B1System for performing data pattern sensitivity compensation using different voltageSANDISK CORP·Filed 2006·Granted Dec 18, 2007·112 cites·9 claims
- 1297US10559588B2Three-dimensional flat inverse NAND memory device and method of making the sameSANDISK TECHNOLOGIES LLC·Filed 2018·Granted Feb 11, 2020·19 cites·20 claims
- 1397US10373969B2Three-dimensional memory device including partially surrounding select gates and fringe field assisted programming thereofSANDISK TECHNOLOGIES LLC·Filed 2018·Granted Aug 6, 2019·29 cites·22 claims
- 1497US10283202B1Reducing disturbs with delayed ramp up of selected word line voltage after pre-charge during programmingSANDISK TECHNOLOGIES LLC·Filed 2017·Granted May 7, 2019·36 cites·20 claims
- 1597US10020314B1Forming memory cell film in stack openingSANDISK TECHNOLOGIES LLC·Filed 2017·Granted Jul 10, 2018·20 cites·17 claims
- 1697US10008271B1Programming of dummy memory cell to reduce charge loss in select gate transistorSANDISK TECHNOLOGIES LLC·Filed 2017·Granted Jun 26, 2018·44 cites·11 claims
- 1797US9959932B1Grouping memory cells into sub-blocks for program speed uniformitySANDISK TECHNOLOGIES LLC·Filed 2017·Granted May 1, 2018·24 cites·16 claims
- 1897US9922992B1Doping channels of edge cells to provide uniform programming speed and reduce read disturbSANDISK TECHNOLOGIES LLC·Filed 2017·Granted Mar 20, 2018·20 cites·9 claims
- 1997US9748266B1Three-dimensional memory device with select transistor having charge trapping gate dielectric layer and methods of making and operating thereofSANDISK TECHNOLOGIES LLC·Filed 2016·Granted Aug 29, 2017·21 cites·24 claims
- 2097US9715937B1Dynamic tuning of first read countermeasuresSANDISK TECHNOLOGIES LLC·Filed 2016·Granted Jul 25, 2017·29 cites·18 claims
- 2197US9640273B1Mitigating hot electron program disturbSANDISK TECHNOLOGIES LLC·Filed 2016·Granted May 2, 2017·52 cites·20 claims
- 2297US9620233B1Word line ramping down scheme to purge residual electronsSANDISK TECHNOLOGIES LLC·Filed 2016·Granted Apr 11, 2017·35 cites·22 claims
- 2397US9559117B2Three-dimensional non-volatile memory device having a silicide source line and method of making thereofSANDISK TECHNOLOGIES INC·Filed 2015·Granted Jan 31, 2017·20 cites·10 claims
- 2497US9490262B1Selective removal of charge-trapping layer for select gate transistor and dummy memory cells in 3D stacked memorySANDISK TECHNOLOGIES INC·Filed 2016·Granted Nov 8, 2016·18 cites·10 claims
- 2597US9466369B1Word line-dependent ramping of pass voltage and program voltage for three-dimensional memorySANDISK TECHNOLOGIES INC·Filed 2015·Granted Oct 11, 2016·49 cites·21 claims
- 2697US9455263B2Three dimensional NAND device with channel contacting conductive source line and method of making thereofSANDISK TECHNOLOGIES INC·Filed 2014·Granted Sep 27, 2016·58 cites·14 claims
- 2797US9412463B1Reducing hot electron injection type of read disturb in 3D non-volatile memory for edge word linesSANDISK TECHNOLOGIES INC·Filed 2015·Granted Aug 9, 2016·48 cites·22 claims
- 2897US9361993B1Method of reducing hot electron injection type of read disturb in memorySANDISK TECHNOLOGIES INC·Filed 2015·Granted Jun 7, 2016·52 cites·21 claims
- 2997US9336892B1Reducing hot electron injection type of read disturb in 3D non-volatile memorySANDISK TECHNOLOGIES INC·Filed 2015·Granted May 10, 2016·71 cites·21 claims
- 3097US9286994B1Method of reducing hot electron injection type of read disturb in dummy memory cellsSANDISK TECHNOLOGIES INC·Filed 2015·Granted Mar 15, 2016·61 cites·20 claims
- 3197US9286987B1Controlling pass voltages to minimize program disturb in charge-trapping memorySANDISK TECHNOLOGIES INC·Filed 2014·Granted Mar 15, 2016·55 cites·13 claims
- 3297US9245642B1Temperature dependent voltage to unselected drain side select transistor during program of 3D NANDSANDISK TECHNOLOGIES INC·Filed 2015·Granted Jan 26, 2016·29 cites·20 claims
- 3397US7433241B2Programming non-volatile memory with reduced program disturb by removing pre-charge dependency on word line dataSANDISK CORP·Filed 2006·Granted Oct 7, 2008·66 cites·34 claims
- 3496US11282582B2Short program verify recovery with reduced programming disturbance in a memory sub-systemMICRON TECHNOLOGY INC·Filed 2020·Granted Mar 22, 2022·5 cites·20 claims
- 3596US10636500B1Reducing read disturb in two-tier memory device by modifying ramp up rate of word line voltages during channel dischargeSANDISK TECHNOLOGIES LLC·Filed 2018·Granted Apr 28, 2020·28 cites·20 claims
- 3696US9941293B1Select transistors with tight threshold voltage in 3D memorySANDISK TECHNOLOGIES LLC·Filed 2016·Granted Apr 10, 2018·12 cites·19 claims
- 3796US9831118B1Reducing neighboring word line in interference using low-k oxideSANDISK TECHNOLOGIES LLC·Filed 2016·Granted Nov 28, 2017·19 cites·20 claims
- 3896US9747992B1Non-volatile memory with customized control of injection type of disturb during read operationsSANDISK TECHNOLOGIES LLC·Filed 2016·Granted Aug 29, 2017·30 cites·20 claims
- 3996US9530785B1Three-dimensional memory devices having a single layer channel and methods of making thereofSANDISK TECHNOLOGIES INC·Filed 2015·Granted Dec 27, 2016·24 cites·25 claims
- 4096US9530506B2NAND boosting using dynamic ramping of word line voltagesSANDISK TECHNOLOGIES INC·Filed 2014·Granted Dec 27, 2016·27 cites·19 claims
- 4196US9368509B2Three-dimensional memory structure having self-aligned drain regions and methods of making thereofSANDISK TECHNOLOGIES INC·Filed 2014·Granted Jun 14, 2016·27 cites·8 claims
- 4296US9355735B1Data recovery in a 3D memory device with a short circuit between word linesSANDISK TECHNOLOGIES INC·Filed 2015·Granted May 31, 2016·32 cites·23 claims
- 4396US9343171B1Reduced erase-verify voltage for first-programmed word line in a memory deviceSANDISK TECHNOLOGIES INC·Filed 2015·Granted May 17, 2016·25 cites·21 claims
- 4496US9299450B1Adaptive increase in control gate voltage of a dummy memory cell to compensate for inadvertent programmingSANDISK TECHNOLOGIES INC·Filed 2015·Granted Mar 29, 2016·25 cites·21 claims
- 4596US9257191B1Charge redistribution during erase in charge trapping memorySANDISK TECHNOLOGIES INC·Filed 2014·Granted Feb 9, 2016·25 cites·21 claims
- 4696US8902658B1Three-dimensional NAND memory with adaptive eraseSANDISK TECHNOLOGIES INC·Filed 2014·Granted Dec 2, 2014·22 cites·17 claims
- 4796US8902661B1Block structure profiling in three dimensional memorySANDISK TECHNOLOGIES INC·Filed 2014·Granted Dec 2, 2014·26 cites·20 claims
- 4896US8902647B1Write scheme for charge trapping memorySANDISK TECHNOLOGIES INC·Filed 2014·Granted Dec 2, 2014·21 cites·21 claims
- 4996US8891308B1Dynamic erase voltage step size selection for 3D non-volatile memorySANDISK TECHNOLOGIES INC·Filed 2013·Granted Nov 18, 2014·29 cites·20 claims
- 5096US8873293B1Dynamic erase voltage step size selection for 3D non-volatile memorySANDISK TECHNOLOGIES INC·Filed 2014·Granted Oct 28, 2014·32 cites·28 claims
Showing the top 50 of 258 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →