Inventor

PANG LIANG

US46 patents

⚠️ This page may combine multiple inventors who share the name “PANG LIANG”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

PANG LIANG

SANDISK TECHNOLOGIES LLC

Memory hole size variation in a 3D stacked memory

Forming memory cell film in stack opening

Three-dimensional memory device with select transistor having charge trapping gate dielectric layer and methods of making and operating thereof

Dynamic tuning of first read countermeasures

Word line ramping down scheme to purge residual electrons

First read solution for memory

Equalizing erase depth in different blocks of memory cells

Dynamic tuning of first read countermeasures

Select transistors with tight threshold voltage in 3D memory

Detecting misalignment in memory array and adjusting read and verify timing parameters on sub-block and block levels

Block health monitoring using threshold voltage of dummy memory cells

Suppressing disturb of select gate transistors during erase in memory

Select transistors with tight threshold voltage in 3D memory

Word line-dependent and temperature-dependent erase depth

Reducing neighboring word line in interference using low-k oxide

High conductivity channel for 3D memory

Method of forming memory cell film

Weak erase prior to read

Non-volatile memory with reduced program speed variation

First read solution for memory

First read solution for memory

Command sequence for first read solution for memory

Amorphous silicon layer in memory device which reduces neighboring word line interference

Reducing charge loss in data memory cell adjacent to dummy memory cell

SANDISK TECHNOLOGIES INC

Selective removal of charge-trapping layer for select gate transistors and dummy memory cells in 3D stacked memory

Word line dependent channel pre-charge for memory

Three-dimensional memory structure having self-aligned drain regions and methods of making thereof

Adaptive increase in control gate voltage of a dummy memory cell to compensate for inadvertent programming

Selective removal of charge-trapping layer for select gate transistor and dummy memory cells in 3D stacked memory

Word line-dependent ramping of pass voltage and program voltage for three-dimensional memory

Programming memory with reduced short-term charge loss

Dummy voltage to reduce first read effect in memory

Alternating refractive index in charge-trapping film in three-dimensional memory

Method and apparatus for refresh programming of memory cells based on amount of threshold voltage downshift

Programming memory with reduced short-term charge loss

Contact for vertical memory with dopant diffusion stopper and associated fabrication method

Read with look-back combined with programming with asymmetric boosting in memory

Reprogramming memory with single program pulse per data state

Avoiding unintentional program or erase of a select gate transistor

Multiple pass programming for memory with different program pulse widths

Modifying program pulses based on inter-pulse period to reduce program noise

Weak erase of a dummy memory cell to counteract inadvertent programming

Efficient reprogramming method for tightening a threshold voltage distribution in a memory device

Dummy word line control scheme for non-volatile memory

Word line-dependent and temperature-dependent pass voltage during programming

Three-dimensional memory structure having self-aligned drain regions and methods of making thereof