P

Inventor

HUANG HUAI

US77 patents
⚠️ This page may combine multiple inventors who share the name “HUANG HUAI”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

IBM

34 patents
US10777411B1Sep 15, 2020

Semiconductor device with selective dielectric deposition

IBM20 citations94
US9966337B1May 8, 2018

Fully aligned via with integrated air gaps

IBM22 citations94
US9911651B1Mar 6, 2018

Skip-vias bypassing a metallization level at minimum pitch

IBM26 citations94
US11152257B2Oct 19, 2021

Barrier-less prefilled via formation

IBM5 citations84
US10366952B2Jul 30, 2019

Semiconductor device including a porous dielectric layer, and method of forming the semiconductor device

IBM5 citations84
US10109579B2Oct 23, 2018

Semiconductor device including a porous dielectric layer, and method of forming the semiconductor device

IBM8 citations84
US10083905B2Sep 25, 2018

Skip-vias bypassing a metallization level at minimum pitch

IBM9 citations84
US9997451B2Jun 12, 2018

Semiconductor device including a porous dielectric layer, and method of forming the semiconductor device

IBM5 citations84
US9960078B1May 1, 2018

Reflow interconnect using Ru

IBM4 citations84
US9837305B1Dec 5, 2017

Forming deep airgaps without flop over

IBM10 citations84
US9793206B1Oct 17, 2017

Heterogeneous metallization using solid diffusion removal of metal interconnects

IBM8 citations84
US9685366B1Jun 20, 2017

Forming chamferless vias using thermally decomposable porefiller

IBM12 citations83
US11756887B2Sep 12, 2023

Backside floating metal for increased capacitance

IBM5 citations75
US11944013B2Mar 26, 2024

Magnetic tunnel junction device with minimum stray field

IBM3 citations74
US11244861B2Feb 8, 2022

Method and structure for forming fully-aligned via

IBM2 citations73
US11158543B2Oct 26, 2021

Silicide formation for source/drain contact in a vertical transport field-effect transistor

IBM2 citations73
US10763160B1Sep 1, 2020

Semiconductor device with selective insulator for improved capacitance

IBM5 citations73
US10692203B2Jun 23, 2020

Measuring defectivity by equipping model-less scatterometry with cognitive machine learning

IBM3 citations73
US10529662B2Jan 7, 2020

Method and structure to construct cylindrical interconnects to reduce resistance

IBM3 citations73
US10361117B2Jul 23, 2019

Selective ILD deposition for fully aligned via with airgap

IBM1 citations73
US9837485B2Dec 5, 2017

High-density MIM capacitors

IBM3 citations73
US9824982B1Nov 21, 2017

Structure and fabrication method for enhanced mechanical strength crack stop

IBM2 citations73
US11199505B2Dec 14, 2021

Machine learning enhanced optical-based screening for in-line wafer testing

IBM2 citations70
US12538553B2Jan 27, 2026

Contact structure for power delivery on semiconductor device

IBM1 citations64
US12424549B2Sep 23, 2025

Skip-level TSV with hybrid dielectric scheme for backside power delivery

IBM1 citations64
US12550713B2Feb 10, 2026

Hybrid buried power rail structure with dual front side and backside processing

IBM0 citations63
US12494428B2Dec 9, 2025

Airgap spacer for power via

IBM0 citations63
US12424557B2Sep 23, 2025

Dual structured buried rail

IBM0 citations63
US12412836B2Sep 9, 2025

Backside power plane

IBM0 citations63
US12334442B2Jun 17, 2025

Dielectric caps for power and signal line routing

IBM0 citations63
US12261056B2Mar 25, 2025

Top via patterning using metal as hard mask and via conductor

IBM0 citations63
US11621189B2Apr 4, 2023

Barrier-less prefilled via formation

IBM0 citations63
US11621199B2Apr 4, 2023

Silicide formation for source/drain contact in a vertical transport field-effect transistor

IBM0 citations63
US11315827B2Apr 26, 2022

Skip via connection between metallization levels

IBM0 citations63

SZ DJI TECHNOLOGY CO LTD

7 patents

TESSERA INC

3 patents

ADEIA SEMICONDUCTOR SOLUTIONS LLC

2 patents

TESSERA LLC

2 patents

BEIJING TIDE PHARMACEUTICAL CO LTD

2 patents

Showing the top 50 of 77 patents by PatentIndex Score.