Inventor
HEINECKE ALEXANDER
US56 patents
Patents
50 patentsUS11163565B2Nov 2, 2021
Systems, methods, and apparatuses for dot production operations
INTEL CORP24 citations98
US10877756B2Dec 29, 2020
Systems, methods, and apparatuses for tile diagonal
INTEL CORP16 citations98
US12039332B2Jul 16, 2024
Systems, methods, and apparatus for matrix move
INTEL CORP7 citations94
US11288068B2Mar 29, 2022
Systems, methods, and apparatus for matrix move
INTEL CORP7 citations94
US11263008B2Mar 1, 2022
Systems, methods, and apparatuses for tile broadcast
INTEL CORP7 citations94
US11200055B2Dec 14, 2021
Systems, methods, and apparatuses for matrix add, subtract, and multiply
INTEL CORP14 citations94
US11093247B2Aug 17, 2021
Systems and methods to load a tile register pair
INTEL CORP22 citations94
US11023235B2Jun 1, 2021
Systems and methods to zero a tile register pair
INTEL CORP22 citations94
US9996350B2Jun 12, 2018
Hardware apparatuses and methods to prefetch a multidimensional block of elements from a multidimensional array
INTEL CORP20 citations94
US10853067B2Dec 1, 2020
Computer processor for higher precision computations using a mixed-precision decomposition of operations
INTEL CORP11 citations93
US11816483B2Nov 14, 2023
Systems, methods, and apparatuses for matrix operations
INTEL CORP11 citations86
US11809869B2Nov 7, 2023
Systems and methods to store a tile register pair to memory
INTEL CORP12 citations86
US11789729B2Oct 17, 2023
Systems and methods for computing dot products of nibbles in two tile operands
INTEL CORP7 citations86
US11669326B2Jun 6, 2023
Systems, methods, and apparatuses for dot product operations
INTEL CORP15 citations86
US11609762B2Mar 21, 2023
Systems and methods to load a tile register pair
INTEL CORP7 citations86
US11645077B2May 9, 2023
Systems and methods to zero a tile register pair
INTEL CORP7 citations85
US10838734B2Nov 17, 2020
Apparatus and method for processing structure of arrays (SoA) and array of structures (AoS) data
INTEL CORP8 citations84
US12260213B2Mar 25, 2025
Systems, methods, and apparatuses for matrix add, subtract, and multiply
INTEL CORP1 citations75
US11768681B2Sep 26, 2023
Apparatus and method for vector multiply and accumulate of packed bytes
INTEL CORP4 citations75
US12314717B2May 27, 2025
Systems, methods, and apparatuses for dot production operations
INTEL CORP0 citations73
US12124847B2Oct 22, 2024
Systems, methods, and apparatuses for tile transpose
INTEL CORP0 citations73
US11590968B2Feb 28, 2023
Methods and apparatus to mitigate hard-braking events
INTEL CORP4 citations73
US11520331B2Dec 6, 2022
Methods and apparatus to update autonomous vehicle perspectives
INTEL CORP6 citations73
US11409525B2Aug 9, 2022
Apparatus and method for vector multiply and accumulate of packed words
INTEL CORP4 citations73
US11354564B2Jun 7, 2022
Tuning of loop orders in blocked dense basic linear algebra subroutines
INTEL CORP4 citations73
US11157384B2Oct 26, 2021
Methods, systems, articles of manufacture and apparatus for code review assistance for dynamically typed languages
INTEL CORP2 citations72
US10853554B2Dec 1, 2020
Systems and methods for determining a configuration for a microarchitecture
INTEL CORP2 citations72
US11544057B2Jan 3, 2023
Computer processor for higher precision computations using a mixed-precision decomposition of operations
INTEL CORP2 citations71
US11126428B2Sep 21, 2021
Computer processor for higher precision computations using a mixed-precision decomposition of operations
INTEL CORP3 citations71
US10802942B2Oct 13, 2020
Methods and apparatus to detect anomalies of a monitored system
INTEL CORP6 citations71
US12293186B2May 6, 2025
Systems and methods to store a tile register pair to memory
INTEL CORP0 citations63
US12282525B2Apr 22, 2025
Systems, methods, and apparatuses for matrix operations
INTEL CORP0 citations63
US12236242B2Feb 25, 2025
Systems and methods to load a tile register pair
INTEL CORP0 citations63
US12182568B2Dec 31, 2024
Systems and methods for computing dot products of nibbles in two tile operands
INTEL CORP0 citations63
US12020000B2Jun 25, 2024
Rounding circuitry for floating-point mantissas
INTEL CORP0 citations63
US12423102B2Sep 23, 2025
Instructions to convert from FP16 to BF8
INTEL CORP0 citations62
US12367045B2Jul 22, 2025
Instructions to convert from FP16 to BF8
INTEL CORP0 citations62
US12353878B2Jul 8, 2025
Apparatuses, methods, and systems for instructions for matrix multiplication instructions
INTEL CORP0 citations62
US10956298B2Mar 23, 2021
Methods and apparatus to detect memory leaks in computing systems
INTEL CORP1 citations62
US12572359B2Mar 10, 2026
8-bit floating point square root and/or reciprocal square root instructions
INTEL CORP0 citations61
US12346692B2Jul 1, 2025
Computer processor for higher precision computations using a mixed-precision decomposition of operations
INTEL CORP0 citations61
US12162480B2Dec 10, 2024
Methods and apparatus to mitigate hard-braking events
INTEL CORP0 citations61
US11868770B2Jan 9, 2024
Computer processor for higher precision computations using a mixed-precision decomposition of operations
INTEL CORP0 citations61
US11669586B2Jun 6, 2023
Systems and methods for combining low-mantissa units to achieve and exceed FP64 emulation of matrix multiplication
INTEL CORP0 citations61
US11475369B2Oct 18, 2022
Methods and apparatus to provide machine assisted programming
INTEL CORP1 citations61
US11263291B2Mar 1, 2022
Systems and methods for combining low-mantissa units to achieve and exceed FP64 emulation of matrix multiplication
INTEL CORP0 citations61
US12229554B2Feb 18, 2025
BFLOAT16 fused multiply instructions
INTEL CORP0 citations60
US11386256B2Jul 12, 2022
Systems and methods for determining a configuration for a microarchitecture
INTEL CORP0 citations60
US10929143B2Feb 23, 2021
Method and apparatus for efficient matrix alignment in a systolic array
INTEL CORP1 citations59
US12554644B2Feb 17, 2026
Hierarchical core valid tracker for cache coherency
INTEL CORP0 citations58
Showing the top 50 of 56 patents by PatentIndex Score.