Systems and methods for computing dot products of nibbles in two tile operands

Abstract

Disclosed embodiments relate to computing dot products of nibbles in tile operands. In one example, a processor includes decode circuitry to decode a tile dot product instruction having fields for an opcode, a destination identifier to identify a M by N destination matrix, a first source identifier to identify a M by K first source matrix, and a second source identifier to identify a K by N second source matrix, each of the matrices containing doubleword elements, and execution circuitry to execute the decoded instruction to perform a flow K times for each element (M,N) of the identified destination matrix to generate eight products by multiplying each nibble of a doubleword element (M,K) of the identified first source matrix by a corresponding nibble of a doubleword element (K,N) of the identified second source matrix, and to accumulate and saturate the eight products with previous contents of the doubleword element (M,N).

What is claimed is: 
     
       1. An apparatus comprising:
 a plurality of memory controllers; 
 a level-two (L2) cache memory coupled to the plurality of memory controllers; and 
 a processor coupled to the plurality of memory controllers, and coupled to the L2 cache memory, the processor having a plurality of cores comprising circuitry to perform operations corresponding to an instruction, the instruction to indicate a first matrix having M rows by K columns of 32-bit elements each having eight 4-bit data elements, a second matrix having K rows by N columns of 32-bit elements each having eight 4-bit data elements, and a third matrix having M rows by N columns, the instruction having a first indicator to indicate whether the 4-bit data elements of the first matrix are signed or unsigned, and a second indicator to indicate whether the 4-bit data elements of the second matrix are signed or unsigned, the operations including to:
 for each row m of the M rows of the first matrix, and for each column n of the N columns of the second matrix:
 for each of K 32-bit elements of the row m of the first matrix:
 multiply eight 4-bit data elements of the 32-bit element of the row m of the first matrix with corresponding ones of eight 4-bit data elements of a corresponding 32-bit element of the column n of the second matrix to generate eight products; and 
 
 store a 32-bit result data element, at a row m of the M rows, and a column n of the N columns, of the third matrix, the 32-bit result data element to be based on accumulation of the eight products generated for each of the K 32-bit elements of the row m of the first matrix, with a 32-bit data element corresponding to the row m of the first matrix and the column n of the second matrix. 
 
 
 
     
     
       2. The apparatus of  claim 1 , wherein the operations further include to perform saturation to generate the 32-bit result data element. 
     
     
       3. The apparatus of  claim 2 , wherein to perform the saturation comprises to perform signed saturation. 
     
     
       4. The apparatus of  claim 1 , wherein K is 4. 
     
     
       5. The apparatus of  claim 4 , wherein M is one of 2, 4, 8, and 16. 
     
     
       6. The apparatus of  claim 1 , wherein the first matrix is to be stored in a plurality of registers of the processor, and wherein the second matrix is to be stored in a plurality of registers of the processor. 
     
     
       7. The apparatus of  claim 1 , further comprising an interconnect interface coupled to the processor. 
     
     
       8. The apparatus of  claim 1 , further comprising a bus controller interface coupled to the processor. 
     
     
       9. The apparatus of  claim 1 , wherein the cores comprise graphics cores. 
     
     
       10. The apparatus of  claim 1 , wherein the cores comprise heterogeneous graphics cores. 
     
     
       11. The apparatus of  claim 1 , further comprising an instruction converter to convert the instruction into one or more instructions of a different instruction set executable by the cores. 
     
     
       12. The apparatus of  claim 1 , wherein the 4-bit data elements of one of the first and second matrices are signed and the 4-bit data elements of another of the first and second matrices are unsigned. 
     
     
       13. An apparatus comprising:
 circuitry to receive an instruction, the instruction to indicate a first matrix having M rows by K columns of 32-bit elements each having eight 4-bit data elements, a second matrix having K rows by N columns of 32-bit elements each having eight 4-bit data elements, and a third matrix having M rows by N columns, the instruction having a first indicator to indicate whether the 4-bit data elements of the first matrix are signed or unsigned, and a second indicator to indicate whether the 4-bit data elements of the second matrix are signed or unsigned; and 
 execution circuitry to perform operations corresponding to the instruction, including to:
 for each row m of the M rows of the first matrix, and for each column n of the N columns of the second matrix:
 for each of K 32-bit elements of the row m of the first matrix:
 multiply eight 4-bit data elements of the 32-bit element of the row m of the first matrix with corresponding ones of eight 4-bit data elements of a corresponding 32-bit element of the column n of the second matrix to generate eight products; and 
 
 store a 32-bit result data element, at a row m of the M rows, and a column n of the N columns, of the third matrix, the 32-bit result data element to be based on accumulation of the eight products generated for each of the K 32-bit elements of the row m of the first matrix, with a 32-bit data element corresponding to the row m of the first matrix and the column n of the second matrix. 
 
 
 
     
     
       14. The apparatus of  claim 13 , wherein the operations further include to perform saturation to generate the 32-bit result data element, wherein the first matrix is to be stored in a plurality of registers, and wherein the second matrix is to be stored in a plurality of registers. 
     
     
       15. The apparatus of  claim 13 , wherein K is 4, and wherein M is one of 2, 4, 8, and 16. 
     
     
       16. The apparatus of  claim 13 , wherein the 4-bit data elements of one of the first and second matrices are signed and the 4-bit data elements of another of the first and second matrices are unsigned. 
     
     
       17. The apparatus of  claim 13 , wherein the circuitry to receive the instruction is to convert the instruction into one or more other instructions. 
     
     
       18. An apparatus comprising:
 an instruction converter to convert a first instruction into one or more other instructions, the first instruction to indicate a first matrix having M rows by K columns of 32-bit elements each having eight 4-bit data elements, a second matrix having K rows by N columns of 32-bit elements each having eight 4-bit data elements, and a third matrix having M rows by N columns, the instruction having a first indicator to indicate whether the 4-bit data elements of the first matrix are signed or unsigned, and a second indicator to indicate whether the 4-bit data elements of the second matrix are signed or unsigned; and 
 execution circuitry to perform operations corresponding to the first instruction, including to:
 for each row m of the M rows of the first matrix, and for each column n of the N columns of the second matrix:
 for each of K 32-bit elements of the row m of the first matrix:
 multiply eight 4-bit data elements of the 32-bit element of the row m of the first matrix with corresponding ones of eight 4-bit data elements of a corresponding 32-bit element of the column n of the second matrix to generate eight products; and 
 
 store a 32-bit result data element, at a row m of the M rows, and a column n of the N columns, of the third matrix, the 32-bit result data element to be based on accumulation of the eight products generated for each of the K 32-bit elements of the row m of the first matrix, with a 32-bit data element corresponding to the row m of the first matrix and the column n of the second matrix. 
 
 
 
     
     
       19. The apparatus of  claim 18 , wherein the first matrix is to be stored in a plurality of registers, and wherein the second matrix is to be stored in a plurality of registers. 
     
     
       20. The apparatus of  claim 19 , wherein K is 4, and wherein M is one of 2, 4, 8, and 16, and wherein the 4-bit data elements of one of the first and second matrices are signed and the 4-bit data elements of another of the first and second matrices are unsigned. 
     
     
       21. The apparatus of  claim 20 , wherein the operations further include to perform saturation to generate the 32-bit result data element.