Inventor · disambiguated record
Amit Gradstein
Also filed as: GRADSTEIN AMIT
126 granted patents·45 pending applications·436 citations·filing 2005–2025
99Inventor score
Top patents by PatentIndex Score
171 records- 0198US11893389B2Systems and methods for performing 16-bit floating-point matrix dot product instructionsINTEL CORP·Filed 2023·Granted Feb 6, 2024·7 cites·24 claims
- 0298US11614936B2Systems and methods for performing 16-bit floating-point matrix dot product instructionsINTEL CORP·Filed 2021·Granted Mar 28, 2023·7 cites·31 claims
- 0398US11609762B2Systems and methods to load a tile register pairINTEL CORP·Filed 2021·Granted Mar 21, 2023·7 cites·26 claims
- 0498US10866786B2Systems and methods for performing instructions to transpose rectangular tilesINTEL CORP·Filed 2018·Granted Dec 15, 2020·27 cites·20 claims
- 0597US12020028B2Apparatuses, methods, and systems for 8-bit floating-point matrix dot product instructionsINTEL CORP·Filed 2020·Granted Jun 25, 2024·7 cites·24 claims
- 0697US11972230B2Matrix transpose and multiplyINTEL CORP·Filed 2020·Granted Apr 30, 2024·9 cites·20 claims
- 0797US11941395B2Apparatuses, methods, and systems for instructions for 16-bit floating-point matrix dot product instructionsINTEL CORP·Filed 2020·Granted Mar 26, 2024·7 cites·24 claims
- 0897US11645077B2Systems and methods to zero a tile register pairINTEL CORP·Filed 2021·Granted May 9, 2023·7 cites·31 claims
- 0997US11403071B2Systems and methods for performing instructions to transpose rectangular tilesINTEL CORP·Filed 2020·Granted Aug 2, 2022·7 cites·21 claims
- 1097US11093247B2Systems and methods to load a tile register pairINTEL CORP·Filed 2017·Granted Aug 17, 2021·22 cites·21 claims
- 1197US10963246B2Systems and methods for performing 16-bit floating-point matrix dot product instructionsINTEL CORP·Filed 2018·Granted Mar 30, 2021·22 cites·20 claims
- 1296US11175891B2Systems and methods to perform floating-point addition with selected roundingINTEL CORP·Filed 2019·Granted Nov 16, 2021·19 cites·20 claims
- 1396US11023235B2Systems and methods to zero a tile register pairINTEL CORP·Filed 2017·Granted Jun 1, 2021·22 cites·25 claims
- 1496US11016731B2Using Fuzzy-Jbit location of floating-point multiply-accumulate resultsINTEL CORP·Filed 2019·Granted May 25, 2021·15 cites·20 claims
- 1595US11809869B2Systems and methods to store a tile register pair to memoryINTEL CORP·Filed 2017·Granted Nov 7, 2023·12 cites·22 claims
- 1695US11669326B2Systems, methods, and apparatuses for dot product operationsINTEL CORP·Filed 2017·Granted Jun 6, 2023·15 cites·21 claims
- 1795US11544058B2Systems, apparatuses, and methods for fused multiply addINTEL CORP·Filed 2021·Granted Jan 3, 2023·2 cites·20 claims
- 1895US11526354B2Systems, apparatuses, and methods for fused multiply addINTEL CORP·Filed 2021·Granted Dec 13, 2022·2 cites·20 claims
- 1994US11816483B2Systems, methods, and apparatuses for matrix operationsINTEL CORP·Filed 2017·Granted Nov 14, 2023·11 cites·21 claims
- 2094US11526353B2Systems, apparatuses, and methods for fused multiply addINTEL CORP·Filed 2021·Granted Dec 13, 2022·2 cites·26 claims
- 2194US11507369B2Systems, apparatuses, and methods for fused multiply addINTEL CORP·Filed 2021·Granted Nov 22, 2022·2 cites·28 claims
- 2294US11372643B2Systems and methods for performing instructions to convert to 16-bit floating-point formatINTEL CORP·Filed 2018·Granted Jun 28, 2022·7 cites·16 claims
- 2394US11169802B2Systems, apparatuses, and methods for fused multiply addINTEL CORP·Filed 2016·Granted Nov 9, 2021·8 cites·10 claims
- 2493US10990397B2Apparatuses, methods, and systems for transpose instructions of a matrix operations acceleratorINTEL CORP·Filed 2019·Granted Apr 27, 2021·14 cites·24 claims
- 2592US11789729B2Systems and methods for computing dot products of nibbles in two tile operandsINTEL CORP·Filed 2017·Granted Oct 17, 2023·7 cites·21 claims
- 2691US11036504B2Systems and methods for performing 16-bit floating-point vector dot product instructionsINTEL CORP·Filed 2020·Granted Jun 15, 2021·2 cites·30 claims
- 2790US9606770B2Multiply add functional unit capable of executing SCALE, ROUND, GETEXP, ROUND, GETMANT, REDUCE, RANGE and CLASS instructionsINTEL CORP·Filed 2014·Granted Mar 28, 2017·9 cites·19 claims
- 2889US11714875B2Apparatuses, methods, and systems for instructions of a matrix operations acceleratorINTEL CORP·Filed 2019·Granted Aug 1, 2023·8 cites·24 claims
- 2989US9465580B2Math circuit for estimating a transcendental functionPINEIRO JOSE-ALEJANDRO·Filed 2011·Granted Oct 11, 2016·24 cites·19 claims
- 3087US11681530B2Apparatuses, methods, and systems for hashing instructionsINTEL CORP·Filed 2022·Granted Jun 20, 2023·1 cites·20 claims
- 3187US11366663B2Systems and methods for performing 16-bit floating-point vector dot product instructionsINTEL CORP·Filed 2018·Granted Jun 21, 2022·3 cites·19 claims
- 3287US10133577B2Vector mask driven clock gating for power efficiency of a processorINTEL CORP·Filed 2012·Granted Nov 20, 2018·8 cites·24 claims
- 3387US8600049B2Method and apparatus for optimizing advanced encryption standard (AES) encryption and decryption in parallel modes of operationGUERON SHAY·Filed 2012·Granted Dec 3, 2013·8 cites·20 claims
- 3486US11567772B2Apparatuses, methods, and systems for hashing instructionsINTEL CORP·Filed 2021·Granted Jan 31, 2023·1 cites·24 claims
- 3585US9619226B2Systems, apparatuses, and methods for performing a horizontal add or subtract in response to a single instructionHAGOG MOSTAFA·Filed 2011·Granted Apr 11, 2017·13 cites·20 claims
- 3685US2025362911A1Systems and methods for performing 16-bit floating-point matrix dot product instructionsINTEL CORP·Filed 2025·Application pending·0 cites
- 3784US9542154B2Fused multiply add operations using bit masksRUBANOVICH SIMON·Filed 2013·Granted Jan 10, 2017·12 cites·18 claims
- 3884US8194854B2Method and apparatus for optimizing advanced encryption standard (AES) encryption and decryption in parallel modes of operationGUERON SHAY·Filed 2008·Granted Jun 5, 2012·11 cites·20 claims
- 3983US10073695B2Floating point round-off amount determination processors, methods, systems, and instructionsINTEL CORP·Filed 2016·Granted Sep 11, 2018·3 cites·22 claims
- 4083US9864602B2Packed rotate processors, methods, systems, and instructionsOULD-AHMED-VALL ELMOUSTAPHA·Filed 2011·Granted Jan 9, 2018·8 cites·22 claims
- 4183US8914430B2Multiply add functional unit capable of executing scale, round, GETEXP, round, GETMANT, reduce, range and class instructionsGRADSTEIN AMIT·Filed 2010·Granted Dec 16, 2014·8 cites·17 claims
- 4282US12307250B2Systems and methods for performing 16-bit floating-point matrix dot product instructionsINTEL CORP·Filed 2023·Granted May 20, 2025·0 cites·20 claims
- 4382US12124846B2Systems, apparatuses, and methods for addition of partial productsINTEL CORP·Filed 2023·Granted Oct 22, 2024·0 cites·7 claims
- 4482US11188335B2Apparatuses, methods, and systems for hashing instructionsINTEL CORP·Filed 2020·Granted Nov 30, 2021·1 cites·24 claims
- 4582US11036509B2Enabling removal and reconstruction of flag operations in a processorINTEL CORP·Filed 2015·Granted Jun 15, 2021·4 cites·18 claims
- 4681US10719316B2Apparatus and method of improved packed integer permute instructionINTEL CORP·Filed 2017·Granted Jul 21, 2020·2 cites·21 claims
- 4781US9448765B2Floating point scaling processors, methods, systems, and instructionsANDERSON CHRISTINA S·Filed 2011·Granted Sep 20, 2016·7 cites·31 claims
- 4881US2025265081A1Systems and methods for computing dot products of nibbles in two tile operandsINTEL CORP·Filed 2024·Application pending·0 cites
- 4979US12399718B2Apparatuses, methods, and systems for hashing instructionsINTEL CORP·Filed 2023·Granted Aug 26, 2025·0 cites·24 claims
- 5079US12236242B2Systems and methods to load a tile register pairINTEL CORP·Filed 2023·Granted Feb 25, 2025·0 cites·20 claims
Showing the top 50 of 171 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →