Inventor

CHEN GUAN-LIN

TW103 patents

⚠️ This page may combine multiple inventors who share the name “CHEN GUAN-LIN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

CHEN GUAN-LIN

TAIWAN SEMICONDUCTOR MFG CO LTD

Recessing STI to increase fin height in fin-first process

Semiconductor device structure

Uniform gate width for nanostructure devices

Gap-insulated semiconductor device

Semiconductor devices with horizontal gate all around structure and methods of forming the same

Tuning tensile strain on FinFET

FinFET structure and method for fabricating the same

Integrated circuit structure with substrate isolation and un-doped channel

Semiconductor device and formation thereof

Uniform gate width for nanostructure devices

Integration of silicon channel nanostructures and silicon-germanium channel nanostructures

Transistor including downward extending silicide

Multi-layer channel structures and methods of fabricating the same in field-effect transistors preliminary class

Self-aligned metal gate for multigate device

Gap-insulated semiconductor device

Integrated circuit with backside trench for metal gate definition

Semiconductor device structure including forksheet transistors and methods of forming the same

Isolation structures and methods of forming the same in field-effect transistors

Hybrid semiconductor device

Self-aligned metal gate for multigate device

Gate isolation for multigate device

Structure and formation method of semiconductor device with stressor

Multi-layer channel structures and methods of fabricating the same in field-effect transistors

Self-aligned spacers for multi-gate devices and method of fabrication thereof

Integration of silicon channel nanostructures and silicon-germanium channel nanostructures

Semiconductor structure and method of fabricating the semiconductor structure

Multi-gate device and related methods

Tuning tensile strain on FinFET

Tuning tensile strain on FinFET

Recessing STI to increase Fin height in Fin-first process

Integrated circuit structure with substrate isolation and un-doped channel

FinFET with buried insulator layer and method for forming

FinFET structure and method for fabricating the same

Isolation structure of fin field effect transistor

Semiconductor device structure and methods of forming the same

Multi-layer channel structures and methods of fabricating the same in field-effect transistors

Semiconductor structure and method of fabricating the semiconductor structure

Uniform gate width for nanostructure devices

Self-aligned metal gate for multigate device

Self-aligned spacers for multi-gate devices and method of fabrication thereof

Field effect transistor with asymmetrical source/drain region and method

Multigate device with air gap spacer and backside rail contact and method of fabricating thereof

Semiconductor devices including horizontal gate-all-around (hGAA) nanostructure transistors and methods of forming

Integration of silicon channel nanostructures and silicon-germanium channel nanostructures

Semiconductor device with gate isolation features and fabrication method of the same

TAIWAN SEMICONDUCTOR MFG

Isolation structure of fin field effect transistor

Fin recess last process for FinFET fabrication

FinFET with buried insulator layer and method for forming

Recessing STI to increase Fin height in Fin-first process

Tuning tensile strain on FinFET