Tuning tensile strain on FinFET

Abstract

A fin field effect transistor (FinFET) having a tunable tensile strain and an embodiment method of tuning tensile strain in an integrated circuit are provided. The method includes forming a source/drain region on opposing sides of a gate region in a fin, forming spacers over the fin, the spacers adjacent to the source/drain regions, depositing a dielectric between the spacers; and performing an annealing process to contract the dielectric, the dielectric contraction deforming the spacers, the spacer deformation enlarging the gate region in the fin.

What is claimed is: 
     
       1. A semiconductor device comprising:
 a first device comprising:
 a first fin; 
 first source/drain regions in the first fin on opposing sides of a first channel region; 
 a first gate electrode overlying the first channel region; and 
 a first dielectric layer on opposing sides of the first gate electrode, the first gate electrode having linear sidewalls; and 
 
 a second device comprising:
 a second fin; 
 second source/drain regions in the second fin on opposing sides of a second channel region; 
 a second gate electrode overlying the second channel region; and 
 a second dielectric layer on opposing sides of the second gate electrode, the second dielectric layer being a contracted dielectric, the second gate electrode having convex sidewalls projecting toward concave sidewalls of the second dielectric layer. 
 
 
     
     
       2. The semiconductor device of  claim 1 , wherein the first device is a p-type metal-oxide-semiconductor (PMOS) device, and the second device comprises an n-type metal-oxide-semiconductor (NMOS) device. 
     
     
       3. The semiconductor device of  claim 1 , further comprising a second spacer interposed between the second gate electrode and the second dielectric layer. 
     
     
       4. The semiconductor device of  claim 3 , further comprising a first spacer interposed between the first gate electrode and the first dielectric layer. 
     
     
       5. The semiconductor device of  claim 1 , wherein the second device has a longer channel than the first device. 
     
     
       6. The semiconductor device of  claim 1 , wherein the first dielectric layer comprises a different material than the second dielectric layer. 
     
     
       7. The semiconductor device of  claim 1 , wherein the second dielectric layer is more dense than the first dielectric layer. 
     
     
       8. A semiconductor device comprising:
 a first fin extending from a substrate; 
 first source/drain regions in the first fin on opposing sides of a first channel region; 
 a first gate over the first channel region; 
 a contracted dielectric disposed over the first source/drain regions; 
 first spacers interposed between the first gate and the contracted dielectric, the first spacers having a concave surface extending toward the contracted dielectric; 
 a second fin extending from the substrate; 
 second source/drain regions in the second fin on opposing sides of a second channel region; 
 a second gate over the second channel region; 
 a dielectric disposed over the second source/drain regions; and 
 second spacers interposed between the second gate and the dielectric, the second spacers having a linear surface facing the dielectric. 
 
     
     
       9. The semiconductor device of  claim 8 , wherein a contour of sidewalls of the contracted dielectric is equivalent to a contour of the first spacers. 
     
     
       10. The semiconductor device of  claim 8 , wherein the contracted dielectric has been reduced in size about 15% to about 18% relative to an original size of the contracted dielectric. 
     
     
       11. The semiconductor device of  claim 8 , wherein the contracted dielectric is vertically aligned with the first source/drain regions. 
     
     
       12. The semiconductor device of  claim 8 , further comprising an interfacial oxide and a high-k dielectric interposed between the first fin and the first gate. 
     
     
       13. The semiconductor device of  claim 8 , wherein the first gate comprises a metal gate electrode. 
     
     
       14. A semiconductor device comprising:
 a first device comprising:
 a first fin; 
 first source/drain regions in the first fin on opposing sides of a first channel region; 
 a first gate electrode overlying the first channel region; and 
 a first dielectric layer on opposing sides of the first gate electrode, the first dielectric layer being a contracted dielectric layer, the first gate electrode having convex sidewalls projecting toward concave sidewalls of the first dielectric layer; 
 
 a second device comprising:
 a second fin; 
 second source/drain regions in the second fin on opposing sides of a second channel region; 
 a second gate electrode overlying the second channel region, sidewalls of the second gate electrode having a different shape than sidewalls of the first gate electrode; and 
 a second dielectric layer on opposing sides of the second gate electrode, the second dielectric layer being uncontracted; and 
 
 an interlayer dielectric layer over the first fin and the second fin, the interlayer dielectric layer extending along sidewalls of the first dielectric layer and the second dielectric layer. 
 
     
     
       15. The semiconductor device of  claim 14 , wherein the second gate electrode has linear sidewalls. 
     
     
       16. The semiconductor device of  claim 14 , wherein the first device is an NMOS device. 
     
     
       17. The semiconductor device of  claim 14 , further comprising spacers interposed between the first gate electrode and the first dielectric layer, the spacers having curved sidewalls facing the first gate electrode. 
     
     
       18. The semiconductor device of  claim 14 , wherein the first dielectric layer and the second dielectric layer are different materials. 
     
     
       19. The semiconductor device of  claim 14 , wherein the first gate electrode has a first height, the second gate electrode has a second height, the first height being different than the second height. 
     
     
       20. The semiconductor device of  claim 14 , wherein the first dielectric layer is denser than the second dielectric layer.