Inventor

NISHII OSAMU

JP46 patents

⚠️ This page may combine multiple inventors who share the name “NISHII OSAMU”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

NISHII OSAMU

HITACHI LTD

Data processor and data processing system having two translation lookaside buffers

Method for prefetching pointer-type data structure and information processing apparatus therefor

Processor system using synchronous dynamic memory

Multiprocessor system having shared memory divided into a plurality of banks with access queues corresponding to each bank

Data processor and data processing system

Multiprocessor cache system having three states for generating invalidating signals upon write accesses

Semiconductor device

Multiprocessor system having distinct data bus and address bus arbiters

Multiprocessor system having a processor invalidating operand cache when lock-accessing

Data processor having two instruction registers connected in cascade and two instruction decoders

Data processor and data processor system having multiple modes of address indexing and operation

Memory system performing fast access to a memory location by omitting transfer of a redundant address

Multi-processor system for invalidating hierarchical cache

Semiconductor integrated circuit device

Low power processor

Processor system using synchronous dynamic memory

Processor system using synchronous dynamic memory

Processor system using synchronous dynamic memory

System LSI having a substrate-bias generation circuit with a substrate-bias control-value storage unit

Semiconductor integrated circuit device and information processing device employing semiconductor integrated circuit device

Static memory containing sense amp and sense amp switching circuit

Static memory containing sense AMP and sense AMP switching circuit

Data processing system

Memory system performing fast access to a memory location by omitting the transfer of a redundant address

Integrated circuit data processor including a control pin for deactivating the driving of a data bus without deactivating that of an address bus

Semiconductor device

Semiconductor integrated circuit device and information processing device employing semiconductor integrated circuit device

RENESAS TECH CORP

Processor for controlling substrate biases in accordance to the operation modes of the processor

Processor system using synchronous dynamic memory

Substituting specified instruction with NOP to functional unit and halting clock pulses to data latches for power saving

Substrate bias switching unit for a low power processor

Processor system using synchronous dynamic memory

Processor system using synchronous dynamic memory

Semiconductor integrated circuit device

Processor system using synchronous dynamic memory

Program counter (PC) relative addressing mode with fast displacement

Halting clock signals to input and result latches in processing path upon fetching of instruction not supported

Memory system performing fast access to a memory location by omitting the transfer of a redundant address

RENESAS ELECTRONICS CORP

Substrate bias switching unit for a low power processor

Substrate bias switching unit for a low power processor

Data processing system to calculate indexes into a branch target address table based on a current operating mode

Lockstepped CPU selection based on failure status

Semiconductor device with output data selection of lockstepped computing elements based on diagnostic information

UCHIYAMA KUNIO

Processor system using synchronous dynamic memory

HITACHI MICRO SYSTEMS INC

Microprocessor including floating point unit with 16-bit fixed length instruction set

NISHII OSAMU

Data processing system with branch target addressing using upper and lower bit permutation