Memory system performing fast access to a memory location by omitting the transfer of a redundant address

Abstract

A data processing system including a processor LSI and a DRAM divided into banks, for increasing a ratio of using a fast operation mode for omitting transfer of a row address to the DRAM and for minimizing the amount of logics external to the processor LSI. The processor LSI includes row address registers for holding recent row addresses corresponding to the banks. The contents of the row address registers are compared with an accessed address by a comparator to check for each bank whether the fast operation mode is possible. As long as the row address does not change in each bank, the fast operation mode can be used, thus making it possible to speed up operations, for example in block copy processing.

1. A data processing system, comprising:
 a data processing unit;  
 a memory which is divided into a plurality of banks such that an access is made to one of said banks at a time;  
 a plurality of address registers coupled to said data processing unit, and corresponding to said plurality of banks;  
 a comparator coupled to at least one of outputs from said address registers; and  
 a controller coupled to said comparator, ;  
 a first line for sending a row address strobe signal, which is shared with the plurality of banks, from the controller to the memory;  
   a second line for sending a column address strobe signal, which is shared with the plurality of banks, from the controller to the memory;    
   a third line for sending a bank signal, which is shared with the plurality of banks, from the controller to the memory;   
 wherein said data processing unit accesses one of said banks, which is specified by the bank signal of the third line, for reading out data, and accesses another bank of said banks for writing data,  
 wherein each of said plurality of address registers holds recently accessed addresses corresponding to said plurality of banks,  
 wherein said comparator compares an access address for a bus access with contents of at least one of said address registers, when said data processing unit issues said bus access, and  
 wherein said controller omits transfer of said access address to said memory in response to an indication of a coincidence by said comparator, when said bus access is a next bus access after a bus access to a different bank, said indication indicating a coincidence between said access address and said contents of said at least one of said address system  registers.  
 
     
     
       2. A data processing system according to  claim 1 , wherein said data processing unit, and said plurality of address registers are integrated in a single processor LSI (Large Scale Integration). 
     
     
       3. A data processing system according to  claim 1 , wherein said access address is a row address. 
     
     
       4. A data processing system according to  claim 1 , wherein said memory is a dynamic memory LSI. 
     
     
       5. A processor LSI comprising:
   a plurality of address terminals for connecting with a main memory LSI, the main memory LSI using a synchronous dynamic memory having a plurality of banks such that an access is made to one of the plurality of banks at a time;        a first external terminal for outputting a row address strobe signal, which is shared with the plurality of banks, to the main memory LSI;        a second external terminal for outputting a column address strobe signal, which is shared with the plurality of banks, to the main memory LSI;        a third external terminal for outputting a bank signal, which is shared with the plurality of banks, to the main memory LSI;        a data processing unit;        a plurality of address registers coupled to said data processing unit and provided corresponding to the banks;        a selector coupled to said plurality of address registers;        a comparator coupled to said selector and said data processing unit; and        a controller coupled to said comparator,        wherein one of the plurality of the banks is specified by the bank signal, which is determined based on information included in a currently accessed address output by said data processing unit, and accessed at one time;        wherein said address registers hold recently accessed addresses,        wherein said selector selects one of said address registers based on the information included in the currently accessed address,        wherein said comparator compares a row address of the currently accessed address with a recently accessed row address held in the address register selected by said selector, and        wherein said controller, responsive to an output from said comparator indicating that the row address of the currently accessed address is the same as the recently accessed row address, omits transfer of said row address of the currently accessed address and allows output of a column address of the currently accessed address from said first terminals.     
     
     
       6. A processor LSI according to  claim 5 , wherein the information included in the currently accessed address is a bank bit for specifying one of the banks. 
     
     
       7. A processor LSI according to  claim 5 , wherein said processor LSI outputs the row address and the column address to the main memory LSI via said terminals by an address multiplex system. 
     
     
       8. A processor LSI according to  claim 5 , wherein said processor LSI arbitrates so that the data processing unit accesses one of the banks for reading out data and accesses the another one of the banks for writing data. 
     
     
       9. A processor LSI according to  claim 5 , wherein said main memory LSI is a synchronous dynamic memory. 
     
     
       10. The processor LSI according to  claim 5 , wherein when the recently accessed address held in one of said plurality of address registers which is selected by said selector is valid and the row address of the currently accessed address is the same as the recently accessed row address, said controller omits transfer of the row address of the currently accessed address and allows outputs of a column address of the currently accessed address from first terminals, and
   wherein when the recently accessed address held in one of said plurality of address registers is invalid, said controller allows output of the row address and column address of the currently accessed address from said first terminals.     
     
     
       11. The processor LSI according to  claim 10 , further comprising:
   a plurality of valid bits provided corresponding to said plurality of address registers, each of said plurality of valid bits having an information which indicates whether the recently accessed address held in each of said plurality of address registers is valid or invalid.     
     
     
       12. The processor LSI according to  claim 5 , wherein said address registers hold the row address of the recently accessed addresses. 
     
     
       13. A processor LSI comprising:
   a plurality of address terminals for connecting with a main memory LSI, the main memory LSI having at least a first bank and a second bank such that an access is made to one of the first and second banks at a time,        a first external terminal for outputting a row address strobe signal, which is shared with the plurality of banks, to the main memory LSI;        a second external terminal for outputting a column address strobe signal which is shared with the plurality of banks, to the main memory LSI;        a third external terminal for outputting a bank signal, which is shared with the plurality of banks, to the main memory LSI;        wherein one of the plurality of the banks to be accessed is specified by the bank signal,        wherein said processor LSI is enabled to perform a first access to the first bank and then perform a second access to the first bank,        wherein when the value of a row address in the first access is different from the value of a row address in the second access, then said processor LSI outputs a row address and a column address from said address terminals, and        wherein when the value of a row address in said first access is identical with the value of a row address in second access, then said processor LSI outputs a column address from said first terminals without outputting a row address.     
     
     
       14. A processor LSI according to  claim 13 , wherein said processor LSI outputs the row address and the column address to the main memory LSI via said terminals by an address multiplex system. 
     
     
       15. A processor LSI according to  claim 13 , wherein the second access immediately follows the first access. 
     
     
       16. A processor LSI according to  claim 13 , wherein said processor LSI is enabled to perform an access to the second bank between the first access and the second access. 
     
     
       17. A processor LSI according to  claim 13 , wherein said processor LSI is enabled to perform a third access to the first bank, then perform a fourth access to the second bank, and thereafter perform a fifth access to the first bank,
   wherein when the value of a row address in the third access is different from the value of a row address in the fifth access, then said processor LSI outputs a row address and a column address from said first terminals in the fifth access, and        wherein when the value of a row address in said third access is identical with the value of a row address in fifth access, then said processor LSI outputs a column address from said first terminals in the fifth access without outputting a row address.     
     
     
       18. A processor LSI according to  claim 17 , wherein said processor LSI outputs the row address and the column address to the main memory LSI via said second terminals by an address multiplex system. 
     
     
       19. A processor LSI according to  claim 13 , further comprising:
   a data processing unit,        wherein said processor LSI is enabled to perform the first and second accesses according to requests by said processor unit.     
     
     
       20. A processor LSI according to  claim 13 , wherein said main memory LSI is a synchronous dynamic memory. 
     
     
       21. The processor LSI according to  claim 13 , further comprising:
   a first address register corresponding to the first bank; and        a second address register corresponding to the second bank,        wherein said first address register holds the value of the row address in the first access,        wherein when the value of the row address held in said first address register is valid and identical with the value of the row address in second access, then said processor LSI outputs the column address from said first terminals without outputting the row address, and        wherein when the value of the row address held in said first address register is invalid, then said processor LSI outputs the row address and the column address from said first terminals.     
     
     
       22. The processor LSI according to  claim 21 , further comprising:
   a first valid bit provided corresponding to said first address register; and        a second valid bit provided corresponding to said second address register,        wherein each of said first and second valid bits has an information indicating whether the value of an address held therein is valid or invalid.     
     
     
       23. A data processing system, comprising:
   a data processing unit;        a memory having a plurality of banks;        a row address strobe signal line coupling said data processing unit and said memory and provided commonly to said plurality of banks;        a column address strobe signal line coupling said data processing unit and said memory and provided commonly to said plurality of banks;        a bank signal line coupling said data processing unit and said memory and provided commonly to said plurality of banks;        a plurality of address registers holding a row address of a recently accessed address; and        selection means for selecting one of said plurality of address registers using information of a specified bit among an access address issued by said data processing unit,        wherein said bank signal line sends a bank control signal for selecting one from said plurality of banks,        wherein when a row address of the access address issued by said data processing unit coincides with the content of the address register selected by said selection means, the row address in the access address issued by said data processing unit is allowed to prevent from being outputted to said memory.     
     
     
       24. A data processing system according to  claim 23 , wherein said specified bit information a bank bit designating one of said plurality of banks. 
     
     
       25. A data processing system according to  claim 23 , wherein said data processing unit, said plurality of address registers and said selection means are included internally of a processor LSI ( Large Scale Integration ). 
     
     
       26. A data processing system according to  claim 23 , wherein when the address register selected by said selection means does not hold a row address of a valid access address, said data processing system sends the row address and column address of said access address to said memory. 
     
     
       27. A data processing system according to  claim 26 , wherein said data processing system has a plurality of valid bits representing that said plurality of address registers respectively hold row addresses of valid access addresses, and judges whether or not said plurality of address registers hold row addresses of valid access addresses, respectively. 
     
     
       28. A data processing system according to  claim 23 , wherein the plurality of banks included in said memory include a first bank and a second bank, and when said data processing unit performs a first access to a first bank of said memory, performs a second access to a second bank of said memory and performs a third access to a third bank of said memory, a row address is not outputted at the third access if the row address for said first access coincides with that for said third access. 
     
     
       29. A data processing system according to  claim 23 , wherein said memory is a dynamic memory LSI, and said plurality of banks are included in one dynamic LSI. 
     
     
       30. A data processing system according to  claim 23 , wherein said memory includes a plurality of memories, said row address strobe signal line, said column address strobe signal line and said bank signal line are provided in common to said plurality of memories. 
     
     
       31. A processor, comprising:
   an address terminal coupled to a synchronous memory having a plurality of banks including a first bank and a second bank;        a first external terminal for outputting a row address strobe signal commonly to said plurality of banks;        a second external terminal for outputting a column address strobe signal commonly to said plurality of banks; and        a third external terminal for outputting a bank signal commonly to said plurality of banks,        wherein said bank signal is a signal for selecting either one of said plurality of banks of said synchronous memory,        wherein when said processor performs a first access to a first bank of said synchronous memory, performs a second access to a second bank of said synchronous memory and performs a third access to said first bank of said synchronous memory, said processor does not output a row address at the third access if the row address for said first access coincides with that for said third access.     
     
     
       32. A processor according to  claim 31 , wherein when following said third access, a fourth access is performed to said second bank, said processor does not output a row address for the fourth access to said address terminal if the row address for said second access coincides with that for said fourth access. 
     
     
       33. A processor according to  claim 31 , wherein said synchronous memory is a dynamic memory. 
     
     
       34. A processor according to  claim 31 , wherein said processor further comprises address registers provided corresponding to said plurality of banks, the address register holding a row address used when the processor has accessed, and when the row address for said first access held in said address register is invalid, said processor outputs said access address to said synchronous memory without omitting. 
     
     
       35. A processor according to  claim 34 , wherein said processor further comprises valid bits provided corresponding to said plurality of address registers, the valid bit representing whether a row address held in a relevant one of said address registers is valid or not, and in said third access, said processor judges whether the row address for said first access is valid or not by examining a corresponding one of said valid bits. 
     
     
       36. A processor according to  claim 31 , wherein said synchronous memory is one LSI, and said plurality of banks are included in said one synchronous memory. 
     
     
       37. A processor according to  claim 31 , wherein said processor outputs said row address strobe signal, said column address strobe signal and said bank signal in common to a plurality of said synchronous memories. 
     
     
       38. An external circuit control LSI comprising:
   a plurality of external terminals coupled to a processor LSI; and        a plurality of second external terminals coupled to a main memory LSI having a plurality of banks including a first bank and a second bank,        wherein said plurality of second external terminals comprises:      an address terminal for outputting an access address;        a terminal for outputting a row address strobe signal commonly to said plurality of banks;        a terminal for outputting a column address strobe signal commonly to said plurality of banks; and        a terminal for outputting a bank signal commonly to said plurality of banks,          wherein said bank signal is a signal for selecting one to be accessed from said plurality of banks, and said external circuit control LSI is enabled to perform a first access to said first bank and thereafter perform a second access to said first bank,        wherein when in said second access, a row address in said second access is different from a row address in said first access, said external circuit control LSI outputs a row address and a column address from said second external terminals,        wherein when in said second access, the row address in said second access is the same as the row address in said first access, said external circuit control LSI outputs the column address from said second external terminals without outputting the row address therefrom.     
     
     
       39. An external circuit control LSI according to  claim 38 , wherein said second access follows immediately after said first access. 
     
     
       40. An external circuit control LSI according to  claim 38 , wherein said external circuit control LSI is enabled to perform a third access to said second bank between said first access and said second access. 
     
     
       41. An external circuit control LSI according to  claim 38 , wherein said external circuit control LSI is enabled to perform a third access to said first bank, and thereafter perform a fourth access to said second bank, and then perform a fifth access to said first bank,
   wherein when a row address in said fifth access is different from a row address in said third access, said external circuit control LSI, in said fifth access, outputs a row address and a column address from said second external terminals, and        wherein when the row address in said fifth access is the same as the row address in said third access, said external circuit control LSI, in said fifth access, outputs the column address from said second external terminals without outputting the row address therefrom.     
     
     
       42. An external circuit control LSI according to  claim 38 , wherein said external circuit control LSI receives a row address and a column address which constitute a current access address through said first external terminals in parallel, and splits the received access address into the row address and the column address and outputs the same to said main memory LSI from said first external terminals. 
     
     
       43. An external circuit control LSI according to  claim 38 , wherein said main memory LSI is a synchronous dynamic memory. 
     
     
       44. An external circuit control LSI according to  claim 38 , wherein said external circuit control LSI further comprises address registers provided corresponding to said plurality of banks, the address register holding a row address used when accessed to any of said plurality of banks, and when the row address for said first access held in said address register is invalid, said external circuit control LSI outputs a row address and a column address to said main memory LSI. 
     
     
       45. An external circuit control LSI according to  claim 44 , wherein said external circuit control LSI further comprises a valid bit representing whether a row address of said first access is valid or not, and judges whether the row address for said first access is valid or not by examining said valid bit. 
     
     
       46. An external circuit control LSI according to  claim 38 , wherein said plurality of banks are included in one main memory LSI. 
     
     
       47. An external circuit control LSI according to  claim 38 , wherein said external circuit control LSI outputs said row address strobe signal, said column address strobe signal and said bank signal to a plurality of said main memory LSI's.