Inventor

OLSON CHRISTOPHER H

US58 patents

⚠️ This page may combine multiple inventors who share the name “OLSON CHRISTOPHER H”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

OLSON CHRISTOPHER H

SUN MICROSYSTEMS INC

Processor including general-purpose and cryptographic functionality in which cryptographic operations are visible to user-specified software

Apparatus and method for implementing a block cipher algorithm

Out-of-order memory transactions in a fine-grain multithreaded/multi-core processor

Apparatus and method to support pipelining of differing-latency instructions in a multithreaded processor

Apparatus and method for implementing a unified hash algorithm pipeline

Synchronization primitives for flexible scheduling of functional unit operations

Thread-based clock enabling in a multi-threaded processor

Apparatus and method for reducing execution latency of floating point operations having special case operands

Register window management using first pipeline to change current window and second pipeline to read operand from old window and write operand to new window

Partitioned shifter for single instruction stream multiple data stream (SIMD) operations

Low latency integer divider and integration with floating point divider and method

Method and apparatus for fast RC4-like encryption

OLSON CHRISTOPHER H

Apparatus and method for implementing instruction support for the data encryption standard (DES) algorithm

Apparatus and method for implementing instruction support for performing a cyclic redundancy check (CRC)

Associating tag to branch instruction to access array storing predicted target addresses for page crossing targets for comparison with resolved address at execution stage

Suppressing branch prediction information update by branch instructions in incorrect speculative execution path

Processor and method for implementing instruction support for hash algorithms

Processor and method providing instruction support for instructions that utilize multiple register windows

Processor and method for implementing instruction support for multiplication of large operands

Division unit with normalization circuit and plural divide engines for receiving instructions when divide engine availability is indicated

Apparatus and method for implementing instruction support for the camellia cipher algorithm

Instruction support for performing montgomery multiplication

Apparatus and method for implementing hardware support for denormalized operands for floating-point divide operations

Handling multi-cycle integer operations for a multi-threaded processor

IBM

Method and system for minimizing branch misprediction penalties within a processor

Floating point arithmetic unit with size efficient pipelined multiply-add architecture

Efficient floating point normalization mechanism

Method and apparatus for floating point normalization

Efficient floating point overflow and underflow detection system

Processor and method for managing execution of an instruction which determine subsequent to dispatch if an instruction is subject to serialization

Method and system for high speed floating point exception enabled operation in a multiscalar processor system

Floating-point processor having post-writeback spill stage

ORACLE AMERICA INC

Enabling on-chip features via efuses

Apparatus and method for implementing a hash algorithm word buffer

Apparatus and method for local operand bypassing for cryptographic instructions

Apparatus and method for cryptographic key expansion

BROOKS JEFFREY S

System and method of bypassing unrounded results in a multiply-add pipeline unit

Processor which implements fused and unfused multiply-add instructions in a pipelined manner

Processor pipeline which implements fused and unfused multiply-add instructions

Mechanism for handling unfused multiply-accumulate accrued exception bits in a processor

LAM RES CORP

Method and device for compensating wafer bias in a plasma processing chamber

Method and apparatus for pressure control in vacuum processors

Method and apparatus for pressure control in vacuum processors

ORACLE INT CORP

Floating point unit with support for variable length numbers

Processing fixed and variable length numbers

Processing fixed and variable length numbers

MOTOROLA INC

Result normalizer and method of operation

GOLLA ROBERT T

Thread fairness on a multi-threaded processor with multi-cycle cryptographic operations

SPRACKLEN LAWRENCE A

Methods and mechanisms to support multiple features for a number of opcodes

JORDAN PAUL J

Register error correction of speculative data in an out-of-order processor