Method and system for high speed floating point exception enabled operation in a multiscalar processor system

Abstract

A method and system are disclosed for implementing floating point exception enabled operation without substantial performance degradation. In a multiscalar processor system, multiple instructions may be issued and executed simultaneously utilizing multiple independent functional units. This is typically accomplished utilizing separate branch, fixed point and floating point processor units. Floating point arithmetic instructions within the floating point processor unit may initiate one of a variety of exceptions associated within invalid operations and as a result of the pipelined nature of floating point processor units an identification of which instruction initiated the exception is not possible. In the described method and system, an associated dummy instruction having a retained instruction address is dispatched to the fixed point processor unit each time a floating point arithmetic instruction is dispatched to the floating point processor unit. Thereafter, the output of each instruction from the floating point processor unit is synchronized with an output of an associated dummy instruction wherein each instruction within the floating point processor unit which initiates a floating point exception may be accurately identified utilizing the retained instruction address of the associated dummy instruction.

We claim: 
     
       1. A method for enabling high speed floating point exception enabled operation in a multiscalar processor system having a floating point processor unit, a fixed point processor unit and means for simultaneously dispatching instructions to multiple processor units, said method comprising the steps of: simultaneously dispatching an associated dummy instruction having a retained instruction address to said fixed point processor unit in response to each arithmetic instruction dispatched to said floating point processor unit;   synchronizing an output of each arithmetic instruction from said floating point processor unit with an output of an associated dummy instruction from said fixed point processor unit wherein each arithmetic instruction within said floating point processor unit which initiates an occurrence of a floating point exception is accurately identified.   
     
     
       2. The method for enabling high speed floating point exception enabled operation in a multiscalar processor system according to claim 1, wherein said step of synchronizing an output of each arithmetic instruction from said floating point processor unit with an output of an associated dummy instruction from said fixed point processor unit comprises the step of delaying an output of an associated dummy instruction from said fixed point processor unit until an occurrence of an output of an arithmetic instruction from said floating point processor unit. 
     
     
       3. The method for enabling high speed floating point exception enabled operation in a multiscalar processor system according to claim 1, wherein said step of synchronizing an output of each arithmetic instruction from said floating point processor unit with an output of an associated dummy instruction from said fixed point processor unit comprises the step of delaying an output of an arithmetic instruction from said floating point processor unit until an occurrence of an output of an associated dummy instruction from said fixed point processor unit. 
     
     
       4. A system for enabling high speed floating point exception enabled operation in a multiscalar processor system having a floating point processor unit, a fixed point processor unit and means for simultaneously dispatching instructions to multiple processor units, said system comprising the steps of: means for simultaneously dispatching an associated dummy instruction having a retained instruction address to said fixed point processor unit in response to each arithmetic instruction dispatched to said floating point processor unit;   means for synchronizing an output of each instruction from said floating point processor unit with an output of an associated dummy instruction from said fixed point processor unit wherein each arithmetic instruction within said floating point processor unit which initiates an occurrence of a floating point exception is accurately identified.   
     
     
       5. The method for high speed floating point exception enabled operation in a multiscalar processor system according to claim 4, wherein said means for synchronizing an output of each arithmetic instruction from said floating point processor unit with an output of an associated dummy instruction from said fixed point processor unit comprises means for delaying an output of an associated dummy instruction from said fixed point processor unit until an occurrence of an output of an arithmetic instruction from said floating point processor unit. 
     
     
       6. The method for high speed floating point exception enabled operation in a multiscalar processor system according to claim 4, wherein said means for synchronizing an output of each arithmetic instruction from said floating point processor unit with an output of an associated dummy instruction from said fixed point processor unit comprises means for delaying an output of an arithmetic instruction from said floating point processor unit until an occurrence of an associated dummy instruction from said fixed point processor unit.