Inventor

BULZACCHELLI JOHN F

US47 patents

⚠️ This page may combine multiple inventors who share the name “BULZACCHELLI JOHN F”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

BULZACCHELLI JOHN F

IBM

Single-flux-quantum probabilistic digitizer

Multi-tap decision feedback equalizer (DFE) architecture eliminating critical timing path for higher-speed operation

Decision feedback equalizer using soft decisions

Decision feedback equalizer (DFE) architecture

Dynamic phased array tapering without phase recalibration

Continuous-time linear equalizer for high-speed receiving unit

Time domain analog multiplication techniques for adjusting tap weights of feed-forward equalizers

Feed-forward equalizer architectures

Single-flux-quantum probabilistic digitizer

Time-to-digital based analog-to-digital converter architecture

Circuits and methods for DFE with reduced area and power consumption

Calibration of sampling phase and aperature errors in multi-phase sampling systems

Transmitter with fully re-assignable segments for reconfigurable FFE taps

Dynamic phased array tapering without phase recalibration

Distributed voltage regulation system for mitigating the effects of IR-drop

Dynamic voltage regulation

Continuous-time linear equalizer for high-speed receiving unit

Feed-forward equalizer architectures

Hybrid superconducting-magnetic memory cell and array

Edge selection techniques for correcting clock duty cycle

Passgate strength calibration techniques for voltage regulators

Dynamic phased array tapering without phase recalibration

Dynamic phased array tapering without phase recalibration

Dynamic phased array tapering without phase recalibration

Power aware equalization in a serial communications link

Edge selection techniques for correcting clock duty cycle

Circuits and methods for DFE with reduced area and power consumption

BULZACCHELLI JOHN F

Dual-loop voltage regulator architecture with high DC accuracy and fast response time

Capacitive level-shifting circuits and methods for adding DC offsets to output of current-integrating amplifier

Sense amplifier-type latch circuits with static bias current for enhanced operating frequency

Hybrid superconducting-magnetic memory cell and array

Hybrid superconducting-magnetic memory cell and array

Circuits and methods for DFE with reduced area and power consumption

Sampled current-integrating decision feedback equalizer and method

Calibration of multiple parallel data communications lines for high skew conditions

Circuits and methods for DFE with reduced area and power consumption

Peaking amplifier with capacitively-coupled parallel input stages

Timing recovery method and apparatus for an input/output bus with link redundancy

AINSPAN HERSCHEL A

Ultra-compact PLL with wide tuning range and low noise

Ultra-compact PLL with wide tuning range and low noise

Optimal dithering of a digitally controlled oscillator with clock dithering for gain and bandwidth control

AGRAWAL ANKUR

High-resolution phase interpolators

High-resolution phase interpolators

Restoring output common-mode of amplifier via capacitive coupling

BEUKEMA TROY J

Analog signal current integrators with tunable peaking function

Globalfoundries

On-chip test for integrated AC coupling capacitors

GLOBALFOUNDRIES INC

Passgate strength calibration techniques for voltage regulators