Edge selection techniques for correcting clock duty cycle

Abstract

Circuits and methods are provided for generating clock signals and correcting duty cycle distortion in clock signals. A circuit for generating a clock signal includes a multiplexer circuit and an edge-triggered flip-flop circuit. The multiplexer circuit selectively outputs one of a plurality of input clock signals. The edge-triggered flip-flop detects a transitioning edge of the input clock signal that is selectively output from the multiplexer circuit, and in response to the detection, samples a logic level of a received data signal, and generates a transition of an output clock signal at an output port of the edge-triggered flip-flop. The multiplexer circuit selectively outputs one of the plurality of input clock signals to a clock signal port of the edge-triggered flip-flop, based on a logic level of the output clock signal at the output port of the edge-triggered flip-flop, which is input to a select control port of the multiplexer circuit.

What is claimed is: 
     
       1. A circuit for generating a clock signal, comprising:
 a multiplexer circuit to selectively output one of a plurality of input clock signals; 
 an edge-triggered flip-flop circuit comprising a clock signal port, a data signal port, and an output port, wherein the clock signal port is directly connected to an output of the multiplexer circuit, wherein the data signal port receives a data signal, and wherein the output port of the edge-triggered flip-flop is directly connected to a select control port of the multiplexer circuit, and 
 a clock phase definition circuit that generates the data signal which is input to the data input port of the edge-triggered flip-flop, wherein the data signal is a clock signal having a frequency equal to a frequency of the input clock signals, 
 wherein the edge-triggered flip-flop detects a transitioning edge of an input clock signal that is selectively output from the multiplexer circuit, and in response to said detection, samples a logic level of the received data signal, and generates a transition of an output clock signal at the output port, and 
 wherein the multiplexer circuit selectively outputs one of the plurality of input clock signals to the clock signal port of the edge-triggered flip-flop, based on a logic level of the output clock signal at the output port of the edge-triggered flip-flop, which output clock signal is directly input to the select control port of the multiplexer circuit. 
 
     
     
       2. The circuit of  claim 1 , wherein the edge-triggered flip-flop circuit detects a rising edge of the input clock signal selectively output from the multiplexer circuit. 
     
     
       3. The circuit of  claim 1 , wherein the edge-triggered flip-flop circuit detects a falling edge of the input clock signal selectively output from the multiplexer circuit. 
     
     
       4. The circuit of  claim 1 , wherein the multiplexer circuit is a 2:1 multiplexer. 
     
     
       5. The circuit of  claim 1 , wherein the clock phase definition circuit comprises a delay circuit that generates a data input signal by delaying at least one of the input clock signals. 
     
     
       6. The circuit of  claim 1 , wherein the edge-triggered flip-flop is an asynchronously resettable edge-triggered flip-flop. 
     
     
       7. The circuit of  claim 1 , wherein the plurality of input clock signals are clock signals with distorted duty cycles, and wherein the circuit corrects the duty cycles of the input clock signals by using the multiplexer circuit to select transitioning edges of the input clock signals that are substantially equally spaced in time, and by using the selected transitioning edges to trigger the edge-triggered flip-flop to generate an output clock signal at the output port which is substantially free of duty cycle distortion. 
     
     
       8. A method for generating a clock signal, comprising:
 selecting between one of a plurality of input clock signals, based on a logic level of an output clock signal; 
 detecting a transitioning edge of the selected one of the plurality of input clock signals; 
 generating a data signal having a frequency equal to a frequency of the plurality of input clock signals; 
 sampling a logic level of the data signal in response to said detecting; 
 changing the logic level of the output clock, based on the sampled logic level of the data signal; and 
 selecting another one of the plurality of input clock signals, in response to said changing of the logic level of the output clock. 
 
     
     
       9. The method of  claim 8 , wherein a sequence of the selecting, detecting, sampling, changing and selecting steps is repeated, wherein a first input clock signal is selected when the output clock signal transitions to a first logic level and wherein a second input clock signal is selected when the output clock signal transitions to a second logic level. 
     
     
       10. The method of  claim 8 , wherein detecting a transitioning edge comprises detecting a rising edge of the selected one of the plurality of input clock signals. 
     
     
       11. The method of  claim 8 , wherein detecting a transitioning edge comprises detecting a falling edge of the selected one of the plurality of input clock signals. 
     
     
       12. The method of  claim 8 , wherein said detecting, sampling, and changing steps are performed by an edge-triggered flip-flop. 
     
     
       13. The method of  claim 12 , wherein the edge-triggered flip-flop is an asynchronously resettable edge-triggered flip-flop. 
     
     
       14. The method of  claim 8 , wherein each of the plurality of input clock signals is generated with a corresponding one of a plurality of identical circuits. 
     
     
       15. The method of  claim 8 , wherein the plurality of input clock signals are clock signals with distorted duty cycles, wherein the method further comprises correcting the duty cycles of the input clock signals by detecting transitioning edges of the input clock signals that are substantially equally spaced in time to generate an output clock signal which is substantially free of duty cycle distortion.