Inventor

GUPTA DINESH

US38 patents

⚠️ This page may combine multiple inventors who share the name “GUPTA DINESH”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

GUPTA DINESH

IBM

Process for producing circuitized layers and multilayer ceramic sub-laminates and composites thereof

Semiconductor microcooler

Pre-patterned substrate layers for being personalized as needed

Method for making ceramic substrates from thin and thick ceramic greensheets

Semiconductor microcooler

Apparatus and method for repairing electronic packages

Method of making a multilayer ceramic product with thin layers

Semiconductor wafer having trenches with varied dimensions for multi-chip modules

Planar wafer level fan-out of multi-chip modules having different size chips

Copper microcooler structure and fabrication

Copper microcooler structure and fabrication

Process for screening features on an electronic substrate with a low viscosity paste

Method of forming a multilayer ceramic substrate with max-punched vias

Direct bonded heterogeneous integration packaging structures

Multilayer ceramic substrates having internal capacitor, and process for producing same

Semiconductor microcooler

Semiconductor microcooler

Three-dimensional microelectronic package with embedded cooling channels

Direct bonded heterogeneous integration packaging structures

Three-dimensional microelectronic package with embedded cooling channels

Screening method for double pass screening

Screening mask having a stress-relieving area

Optical assemblies for transmitting and manipulating optical beams

CADENCE DESIGN SYSTEMS INC

Flow methodology for single pass parallel hierarchical timing closure of integrated circuit designs

System and method of generating hierarchical block-level timing constraints from chip-level timing constraints

Multi-phase models for timing closure of integrated circuit designs

Machine readable products for single pass parallel hierarchical timing closure of integrated circuit designs

GOLDMAN SACHS & CO LLC

Generative machine learning with retriever having reconfigurable sequence of rankers

Hybrid language model architecture for API orchestration including chain of thought

Data generation and retraining techniques for fine-tuning of embedding models for efficient data retrieval

GUPTA DINESH

Multi-phase models for timing closure of integrated circuit designs

Optical assemblies for transmitting and manipulating optical beams

BHARDWAJ VIVEK

Methods for single pass parallel hierarchical timing closure of integrated circuit designs

Systems for single pass parallel hierarchical timing closure of integrated circuit designs

TRANSWITCH CORP

Combined hardware and software implementation of link capacity adjustment scheme (LCAS) in SONET (synchronous optical network) virtual concatenation (VCAT)

Methods and apparatus for deskewing VCAT/LCAS members

UNITED TECHNOLOGIES CORP

Refractory metal core coatings

LEVITSKY OLEG

Circuit design system and method of generating hierarchical block-level timing constraints from chip-level timing constraints