Inventor
KOH CHAO-MING
TW29 patents
⚠️ This page may combine multiple inventors who share the name “KOH CHAO-MING”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
VANGUARD INT SEMICONDUCT CORP
21 patentsUS5554557ASep 10, 1996
Method for fabricating a stacked capacitor with a self aligned node contact in a memory cell
VANGUARD INT SEMICONDUCT CORP493 citations99
US6391722B1May 21, 2002
Method of making nonvolatile memory having high capacitive coupling ratio
VANGUARD INT SEMICONDUCT CORP87 citations98
US6555434B2Apr 29, 2003
Nonvolatile memory device and manufacturing method thereof
VANGUARD INT SEMICONDUCT CORP21 citations92
US6060353AMay 9, 2000
Method of forming a ring shaped storage node structure for a DRAM capacitor structure
VANGUARD INT SEMICONDUCT CORP21 citations92
US5920775AJul 6, 1999
Method for forming a storage capacitor within an integrated circuit
VANGUARD INT SEMICONDUCT CORP31 citations92
US5807782ASep 15, 1998
Method of manufacturing a stacked capacitor having a fin-shaped storage electrode on a dynamic random access memory cell
VANGUARD INT SEMICONDUCT CORP24 citations92
US5686337ANov 11, 1997
Method for fabricating stacked capacitors in a DRAM cell
VANGUARD INT SEMICONDUCT CORP54 citations92
US6010942AJan 4, 2000
Post chemical mechanical polishing, clean procedure, used for fabrication of a crown shaped capacitor structure
VANGUARD INT SEMICONDUCT CORP40 citations88
US5665623ASep 9, 1997
Method of fabricating totally self-aligned contacts for dynamic randomaccess memory cells
VANGUARD INT SEMICONDUCT CORP28 citations86
US5770510AJun 23, 1998
Method for manufacturing a capacitor using non-conformal dielectric
VANGUARD INT SEMICONDUCT CORP20 citations83
US5674773AOct 7, 1997
Method for planarizing high step-height integrated circuit structures
VANGUARD INT SEMICONDUCT CORP15 citations74
US5597764AJan 28, 1997
Method of contact formation and planarization for semiconductor processes
VANGUARD INT SEMICONDUCT CORP11 citations73
US5729042AMar 17, 1998
Raised fuse structure for laser repair
VANGUARD INT SEMICONDUCT CORP6 citations67
US6258663B1Jul 10, 2001
Method for forming storage node
VANGUARD INT SEMICONDUCT CORP9 citations66
US5804489ASep 8, 1998
Method of manufacturing a crown shape capacitor in semiconductor memory using a single step etching
VANGUARD INT SEMICONDUCT CORP4 citations62
US5910678AJun 8, 1999
Raised fuse structure for laser repair
VANGUARD INT SEMICONDUCT CORP4 citations56
US6446252B1Sep 3, 2002
Photomask method for making the same capacitor cell area near outmost cell arrays
VANGUARD INT SEMICONDUCT CORP1 citations51
US7217616B2May 15, 2007
Non-volatile memory cell and method of forming the same
VANGUARD INT SEMICONDUCT CORP0 citations47
US7115938B2Oct 3, 2006
Non-volatile memory cell and method of forming the same
VANGUARD INT SEMICONDUCT CORP0 citations47
US7092600B2Aug 15, 2006
Method for fabricating Fiber Bragg Grating elements and planar light circuits made thereof
VANGUARD INT SEMICONDUCT CORP0 citations45
US6978066B2Dec 20, 2005
Method for fabricating fiber bragg grating elements and planar light circuits made thereof
VANGUARD INT SEMICONDUCT CORP0 citations45
IND TECH RES INST
5 patentsUS5464782ANov 7, 1995
Method to ensure isolation between source-drain and gate electrode using self aligned silicidation
IND TECH RES INST61 citations96
US5429979AJul 4, 1995
Method of forming a dram cell having a ring-type stacked capacitor
IND TECH RES INST27 citations92
US5364813ANov 15, 1994
Stacked DRAM poly plate capacitor
IND TECH RES INST31 citations92
US5286608AFeb 15, 1994
TiOx as an anti-reflection coating for metal lithography
IND TECH RES INST40 citations92
US6218710B1Apr 17, 2001
Method to ensure isolation between source-drain and gate electrode using self aligned silicidation
IND TECH RES INST4 citations63