Non-volatile memory cell and method of forming the same

Abstract

A non-volatile memory cell comprising a transistor and two plane capacitors. In the memory cell, a switching device is disposed on a substrate, a first plane capacitor having a first doped region and a second plane capacitor having a second doped region. The switching device and the first and second plane capacitors share a common ploysilicon floating gate configured to retain charge as a result of programming the memory cell. The memory cell is configured to be erased by tunneling between the first doped region and the common ploysilicon floating gate without causing junction breakdown within the memory cell. The first and second doped regions are formed in the substrate before forming the common ploysilicon floating gate such that the capacitance of the first and second plane capacitors are constant when the memory cell operates within an operating voltage range.

1. A non-volatile memory cell, comprising:
 a switching device disposed on a substrate; 
 a first plane capacitor having a first heavily doped region coupled to a word line; and 
 a second plane capacitor having a second heavily doped region coupled to an erase pin, wherein the switching device, the first plane capacitor and the second capacitor share a common polysilicon floating gate retaining charge as a result of programming the memory cell; the memory cell is erased by tunneling between the first doped region and the common polysilicon floating gate without causing junction breakdown within the memory cell; and the first and second heavily doped regions are formed in the substrate before forming the common polysilicon floating gate such that the capacitance of the first and second plane capacitors are constant when the memory cell operates within in an operating voltage range. 
 
   
   
     2. The non-volatile memory cell as claimed in  claim 1 , wherein the switching device is an NMOS transistor. 
   
   
     3. The non-volatile memory cell as claimed in  claim 1 , wherein the first heavily doped region is a bottom electrode of the first plane capacitor. 
   
   
     4. The non-volatile memory cell as claimed in  claim 3 , wherein the second heavily doped region is a bottom electrode of the second plane capacitor. 
   
   
     5. A non-volatile memory cell, comprising:
 a switching device; 
 a first plane capacitor having a bottom electrode coupled to a word line; and 
 a second plane capacitor having a bottom electrode coupled to an erase pin, wherein the switching device, the first plane capacitor and the second capacitor share a common polysilicon floating gate retaining charge as a result of programming the memory cell; the memory cell is erased by tunneling between the bottom electrode and the common polysilicon floating gate without causing any junction breakdown within the memory cell; and capacitance of the first and second plane capacitors are constant when the memory cell operates within in an operating voltage range. 
 
   
   
     6. The non-volatile memory cell as claimed in  claim 5 , wherein the switching device is an NMOS transistor.