Inventor

MANIPATRUNI SASIKANTH

US417 patents

⚠️ This page may combine multiple inventors who share the name “MANIPATRUNI SASIKANTH”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

MANIPATRUNI SASIKANTH

KEPLER COMPUTING INC

Pulsing scheme for a ferroelectric memory bit-cell to minimize read or write disturb effect and refresh logic

Doped polar layers and semiconductor device incorporating same

3D stack of accelerator die and multi-core processor die

Stacked ferroelectric non-planar capacitors in a memory bit-cell

3D integrated ultra high-bandwidth multi-stacked memory

Artificial intelligence processor with three-dimensional stacked memory

3D integrated ultra high-bandwidth memory

High-density low voltage non-volatile differential memory bit-cell with shared plate-line

Low power ferroelectric based majority logic gate adder

High-density low voltage non-volatile differential memory bit-cell with shared plate line

B-site doped perovskite layers and semiconductor device incorporating same

Doped polar layers and semiconductor device incorporating same

Ferroelectric or paraelectric memory and logic chiplet with thermal management in a multi-dimensional packaging

Doped polar layers and semiconductor device incorporating same

Common mode compensation for non-linear polar material based 1T1C memory bit-cell

Non-linear polar material based memory bit-cell with multi-level storage by applying different voltage levels

Writing scheme for 1TnC ferroelectric memory bit-cell with plate-lines parallel to a bit-line and with individual switches on the plate-lines of the bit-cell

High-density low voltage multi-element ferroelectric gain memory bit-cell with pillar capacitors

Stacked ferroelectric planar capacitors in a memory bit-cell

Method of forming stacked ferroelectric non- planar capacitors in a memory bit-cell

Doped polar layers and semiconductor device incorporating same

Doped polar layers and semiconductor device incorporating same

Doped polar layers and semiconductor device incorporating same

Doped polar layers and semiconductor device incorporating same

Doped polar layers and semiconductor device incorporating same

Doped polar layers and semiconductor device incorporating same

Doped polar layers and semiconductor device incorporating same

Ferroelectric or paraelectric based sequential circuit

Doped polar layers and semiconductor device incorporating same

Doped polar layers and semiconductor device incorporating same

Doped polar layers and semiconductor device incorporating same

Low power ferroelectric based majority logic gate carry propagate and serial adder

Majority logic gate with non-linear input capacitors

Artificial intelligence processor with three-dimensional stacked memory

Majority logic gate based sequential circuit

Majority logic gate fabrication

Ferroelectric device film stacks with texturing layer, and method of forming such

Low latency and high bandwidth artificial intelligence processor

3D stack of split graphics processing logic dies

Ferroelectric memory chiplet in a multi-dimensional packaging with I/O switch embedded in a substrate or interposer

Ferroelectric memory chiplet in a multi-dimensional packaging

Method and apparatus for heuristic-based power gating of non-CMOS logic and CMOS based logic

Method and apparatus for managing power in a multi-dimensional packaging

Method and apparatus for managing power of ferroelectric or paraelectric logic and CMOS based logic

Dual hydrogen barrier layer for trench capacitors integrated with low density film for logic structures and methods of fabrication

Doped polar layers and semiconductor device incorporating same

Doped polar layers and semiconductor device incorporating same

INTEL CORP

Spin logic with spin hall electrodes and charge interconnects

Binary, ternary and bit serial compute-in-memory circuits

Nanomagnetic devices switched with a spin hall effect