Inventor

DOKANIA RAJEEV KUMAR

US254 patents

Patents

50 patents

US11482270B1Oct 25, 2022

Pulsing scheme for a ferroelectric memory bit-cell to minimize read or write disturb effect and refresh logic

KEPLER COMPUTING INC70 citations99

US11694940B1Jul 4, 2023

High-density low voltage non-volatile differential memory bit-cell with shared plate-line

KEPLER COMPUTING INC47 citations98

US10944404B1Mar 9, 2021

Low power ferroelectric based majority logic gate adder

KEPLER COMPUTING INC57 citations98

US10847201B2Nov 24, 2020

High-density low voltage non-volatile differential memory bit-cell with shared plate line

KEPLER COMPUTING INC70 citations98

US11791233B1Oct 17, 2023

Ferroelectric or paraelectric memory and logic chiplet with thermal management in a multi-dimensional packaging

KEPLER COMPUTING INC8 citations94

US11696451B1Jul 4, 2023

Common mode compensation for non-linear polar material based 1T1C memory bit-cell

KEPLER COMPUTING INC9 citations94

US11545204B1Jan 3, 2023

Non-linear polar material based memory bit-cell with multi-level storage by applying different voltage levels

KEPLER COMPUTING INC10 citations94

US11538514B1Dec 27, 2022

Writing scheme for 1TnC ferroelectric memory bit-cell with plate-lines parallel to a bit-line and with individual switches on the plate-lines of the bit-cell

KEPLER COMPUTING INC10 citations94

US11532635B1Dec 20, 2022

High-density low voltage multi-element ferroelectric gain memory bit-cell with pillar capacitors

KEPLER COMPUTING INC10 citations94

US11521667B1Dec 6, 2022

Stacked ferroelectric planar capacitors in a memory bit-cell

KEPLER COMPUTING INC11 citations94

US11501813B1Nov 15, 2022

Method of forming stacked ferroelectric non- planar capacitors in a memory bit-cell

KEPLER COMPUTING INC11 citations94

US11303280B1Apr 12, 2022

Ferroelectric or paraelectric based sequential circuit

KEPLER COMPUTING INC12 citations94

US11283453B2Mar 22, 2022

Low power ferroelectric based majority logic gate carry propagate and serial adder

KEPLER COMPUTING INC13 citations94

US11277137B1Mar 15, 2022

Majority logic gate with non-linear input capacitors

KEPLER COMPUTING INC20 citations94

US11171115B2Nov 9, 2021

Artificial intelligence processor with three-dimensional stacked memory

KEPLER COMPUTING INC27 citations94

US11165430B1Nov 2, 2021

Majority logic gate based sequential circuit

KEPLER COMPUTING INC32 citations94

US10951213B1Mar 16, 2021

Majority logic gate fabrication

KEPLER COMPUTING INC21 citations94

US11836102B1Dec 5, 2023

Low latency and high bandwidth artificial intelligence processor

KEPLER COMPUTING INC18 citations92

US12243797B1Mar 4, 2025

3D stack of split graphics processing logic dies

KEPLER COMPUTING INC5 citations86

US12086410B1Sep 10, 2024

Ferroelectric memory chiplet in a multi-dimensional packaging with I/O switch embedded in a substrate or interposer

KEPLER COMPUTING INC7 citations86

US12079475B1Sep 3, 2024

Ferroelectric memory chiplet in a multi-dimensional packaging

KEPLER COMPUTING INC13 citations86

US12026034B1Jul 2, 2024

Method and apparatus for heuristic-based power gating of non-CMOS logic and CMOS based logic

KEPLER COMPUTING INC3 citations86

US12019492B1Jun 25, 2024

Method and apparatus for managing power in a multi-dimensional packaging

KEPLER COMPUTING INC3 citations86

US12001266B1Jun 4, 2024

Method and apparatus for managing power of ferroelectric or paraelectric logic and CMOS based logic

KEPLER COMPUTING INC3 citations86

US11955512B1Apr 9, 2024

Dual hydrogen barrier layer for trench capacitors integrated with low density film for logic structures and methods of fabrication

KEPLER COMPUTING INC3 citations86

US11899613B1Feb 13, 2024

Method and apparatus to process an instruction for a distributed logic having tightly coupled accelerator core and processor core in a multi-dimensional packaging

KEPLER COMPUTING INC6 citations86

US11844223B1Dec 12, 2023

Ferroelectric memory chiplet as unified memory in a multi-dimensional packaging

KEPLER COMPUTING INC8 citations86

US11829699B1Nov 28, 2023

Method to segregate logic and memory into separate dies for thermal management in a multi-dimensional packaging

KEPLER COMPUTING INC5 citations86

US11764190B1Sep 19, 2023

3D stacked compute and memory with copper pillars

KEPLER COMPUTING INC4 citations86

US11670352B1Jun 6, 2023

Apparatus and method for endurance of non-volatile memory banks via wear leveling and outlier compensation

KEPLER COMPUTING INC7 citations86

US11664371B1May 30, 2023

Multi-function threshold gate with adaptive threshold and stacked planar paraelectric capacitors

KEPLER COMPUTING INC7 citations86

US11652487B1May 16, 2023

Parallel pull-up and pull-down networks controlled asynchronously by majority gate or minority gate logic

KEPLER COMPUTING INC7 citations86

US11641205B1May 2, 2023

Reset mechanism for a chain of majority or minority gates having paraelectric material

KEPLER COMPUTING INC6 citations86

US11521666B1Dec 6, 2022

High-density low voltage multi-element ferroelectric gain memory bit-cell with planar capacitors

KEPLER COMPUTING INC6 citations86

US11418197B1Aug 16, 2022

Majority logic gate having paraelectric input capacitors and a local conditioning mechanism

KEPLER COMPUTING INC10 citations86

US11381244B1Jul 5, 2022

Low power ferroelectric based majority logic gate multiplier

KEPLER COMPUTING INC6 citations86

US11374575B1Jun 28, 2022

Majority logic gate with non-linear input capacitors and conditioning logic

KEPLER COMPUTING INC8 citations86

US11295796B1Apr 5, 2022

Apparatus and method for endurance of non-volatile memory banks via wear leveling and random swap injection

KEPLER COMPUTING INC6 citations86

US11748537B1Sep 5, 2023

Computer-aided design tool for logic synthesis of a mix of CMOS gates and majority and minority logic circuits

KEPLER COMPUTING INC4 citations85

US11841757B1Dec 12, 2023

Method and apparatus for cycle-by-cycle clock gating of ferroelectric or paraelectric logic and CMOS based logic

KEPLER COMPUTING INC3 citations84

US11837268B1Dec 5, 2023

Multi-element ferroelectric gain memory bit-cell having stacked and folded planar capacitors with lateral offset

KEPLER COMPUTING INC3 citations84

US11770936B1Sep 26, 2023

Stack of planar capacitors including capacitors with non-linear polar material and linear dielectric for common mode compensation in a memory bit-cell

KEPLER COMPUTING INC3 citations84

US11735245B1Aug 22, 2023

Read scheme for multi-element gain ferroelectric memory bit-cell with plate-line parallel to word-line to minimize read or write disturb effects

KEPLER COMPUTING INC3 citations84

US11532344B1Dec 20, 2022

Reading scheme for 1TNC ferroelectric memory bit-cell with plate-line parallel to bit-line and with individual switches on plate-lines of the bit-cell

KEPLER COMPUTING INC2 citations84

US11527277B1Dec 13, 2022

High-density low voltage ferroelectric memory bit-cell

KEPLER COMPUTING INC3 citations84

Showing the top 50 of 254 patents by PatentIndex Score.

DOKANIA RAJEEV KUMAR

Patents

Pulsing scheme for a ferroelectric memory bit-cell to minimize read or write disturb effect and refresh logic

3D stack of accelerator die and multi-core processor die

Stacked ferroelectric non-planar capacitors in a memory bit-cell

3D integrated ultra high-bandwidth multi-stacked memory

Artificial intelligence processor with three-dimensional stacked memory

3D integrated ultra high-bandwidth memory

High-density low voltage non-volatile differential memory bit-cell with shared plate-line

Low power ferroelectric based majority logic gate adder

High-density low voltage non-volatile differential memory bit-cell with shared plate line

Ferroelectric or paraelectric memory and logic chiplet with thermal management in a multi-dimensional packaging

Common mode compensation for non-linear polar material based 1T1C memory bit-cell

Non-linear polar material based memory bit-cell with multi-level storage by applying different voltage levels

Writing scheme for 1TnC ferroelectric memory bit-cell with plate-lines parallel to a bit-line and with individual switches on the plate-lines of the bit-cell

High-density low voltage multi-element ferroelectric gain memory bit-cell with pillar capacitors

Stacked ferroelectric planar capacitors in a memory bit-cell

Method of forming stacked ferroelectric non- planar capacitors in a memory bit-cell

Ferroelectric or paraelectric based sequential circuit

Low power ferroelectric based majority logic gate carry propagate and serial adder

Majority logic gate with non-linear input capacitors

Artificial intelligence processor with three-dimensional stacked memory

Majority logic gate based sequential circuit

Majority logic gate fabrication

Low latency and high bandwidth artificial intelligence processor

3D stack of split graphics processing logic dies

Ferroelectric memory chiplet in a multi-dimensional packaging with I/O switch embedded in a substrate or interposer

Ferroelectric memory chiplet in a multi-dimensional packaging

Method and apparatus for heuristic-based power gating of non-CMOS logic and CMOS based logic

Method and apparatus for managing power in a multi-dimensional packaging

Method and apparatus for managing power of ferroelectric or paraelectric logic and CMOS based logic

Dual hydrogen barrier layer for trench capacitors integrated with low density film for logic structures and methods of fabrication

Method and apparatus to process an instruction for a distributed logic having tightly coupled accelerator core and processor core in a multi-dimensional packaging

Ferroelectric memory chiplet as unified memory in a multi-dimensional packaging

Method to segregate logic and memory into separate dies for thermal management in a multi-dimensional packaging

3D stacked compute and memory with copper pillars

Apparatus and method for endurance of non-volatile memory banks via wear leveling and outlier compensation

Multi-function threshold gate with adaptive threshold and stacked planar paraelectric capacitors

Parallel pull-up and pull-down networks controlled asynchronously by majority gate or minority gate logic

Reset mechanism for a chain of majority or minority gates having paraelectric material

High-density low voltage multi-element ferroelectric gain memory bit-cell with planar capacitors

Majority logic gate having paraelectric input capacitors and a local conditioning mechanism

Low power ferroelectric based majority logic gate multiplier

Majority logic gate with non-linear input capacitors and conditioning logic

Apparatus and method for endurance of non-volatile memory banks via wear leveling and random swap injection

Computer-aided design tool for logic synthesis of a mix of CMOS gates and majority and minority logic circuits

Method and apparatus for cycle-by-cycle clock gating of ferroelectric or paraelectric logic and CMOS based logic

Multi-element ferroelectric gain memory bit-cell having stacked and folded planar capacitors with lateral offset

Stack of planar capacitors including capacitors with non-linear polar material and linear dielectric for common mode compensation in a memory bit-cell

Read scheme for multi-element gain ferroelectric memory bit-cell with plate-line parallel to word-line to minimize read or write disturb effects

Reading scheme for 1TNC ferroelectric memory bit-cell with plate-line parallel to bit-line and with individual switches on plate-lines of the bit-cell

High-density low voltage ferroelectric memory bit-cell