Inventor

MATHURIYA AMRITA

US274 patents

⚠️ This page may combine multiple inventors who share the name “MATHURIYA AMRITA”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

MATHURIYA AMRITA

KEPLER COMPUTING INC

Pulsing scheme for a ferroelectric memory bit-cell to minimize read or write disturb effect and refresh logic

3D stack of accelerator die and multi-core processor die

Stacked ferroelectric non-planar capacitors in a memory bit-cell

3D integrated ultra high-bandwidth multi-stacked memory

Artificial intelligence processor with three-dimensional stacked memory

3D integrated ultra high-bandwidth memory

Low power ferroelectric based majority logic gate adder

Ferroelectric or paraelectric memory and logic chiplet with thermal management in a multi-dimensional packaging

Common mode compensation for non-linear polar material based 1T1C memory bit-cell

Non-linear polar material based memory bit-cell with multi-level storage by applying different voltage levels

Writing scheme for 1TnC ferroelectric memory bit-cell with plate-lines parallel to a bit-line and with individual switches on the plate-lines of the bit-cell

High-density low voltage multi-element ferroelectric gain memory bit-cell with pillar capacitors

Stacked ferroelectric planar capacitors in a memory bit-cell

Method of forming stacked ferroelectric non- planar capacitors in a memory bit-cell

Ferroelectric or paraelectric based sequential circuit

Low power ferroelectric based majority logic gate carry propagate and serial adder

Majority logic gate with non-linear input capacitors

Artificial intelligence processor with three-dimensional stacked memory

Majority logic gate based sequential circuit

Majority logic gate fabrication

Low latency and high bandwidth artificial intelligence processor

3D stack of split graphics processing logic dies

Ferroelectric memory chiplet in a multi-dimensional packaging with I/O switch embedded in a substrate or interposer

Ferroelectric memory chiplet in a multi-dimensional packaging

Method and apparatus for heuristic-based power gating of non-CMOS logic and CMOS based logic

Method and apparatus for managing power in a multi-dimensional packaging

Method and apparatus for managing power of ferroelectric or paraelectric logic and CMOS based logic

Dual hydrogen barrier layer for trench capacitors integrated with low density film for logic structures and methods of fabrication

Method and apparatus to process an instruction for a distributed logic having tightly coupled accelerator core and processor core in a multi-dimensional packaging

Ferroelectric memory chiplet as unified memory in a multi-dimensional packaging

Method to segregate logic and memory into separate dies for thermal management in a multi-dimensional packaging

3D stacked compute and memory with copper pillars

Apparatus and method for endurance of non-volatile memory banks via wear leveling and outlier compensation

Multi-function threshold gate with adaptive threshold and stacked planar paraelectric capacitors

Parallel pull-up and pull-down networks controlled asynchronously by majority gate or minority gate logic

Reset mechanism for a chain of majority or minority gates having paraelectric material

High-density low voltage multi-element ferroelectric gain memory bit-cell with planar capacitors

Majority logic gate having paraelectric input capacitors and a local conditioning mechanism

Low power ferroelectric based majority logic gate multiplier

Majority logic gate with non-linear input capacitors and conditioning logic

Apparatus and method for endurance of non-volatile memory banks via wear leveling and random swap injection

Memory devices with dual encapsulation layers and methods of fabrication

Computer-aided design tool for logic synthesis of a mix of CMOS gates and majority and minority logic circuits

Method and apparatus for cycle-by-cycle clock gating of ferroelectric or paraelectric logic and CMOS based logic

Multi-element ferroelectric gain memory bit-cell having stacked and folded planar capacitors with lateral offset

INTEL CORP

Binary, ternary and bit serial compute-in-memory circuits

Compute in memory circuits with multi-Vdd arrays and/or analog multipliers

Compute in memory circuits with time-to-digital computation

Binary, ternary and bit serial compute-in-memory circuits

In-memory multiply and accumulate with global charge-sharing