Inventor
YU MO-CHIUN
TW26 patents
⚠️ This page may combine multiple inventors who share the name “YU MO-CHIUN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
TAIWAN SEMICONDUCTOR MFG
24 patentsUS6225167B1May 1, 2001
Method of generating multiple oxide thicknesses by one oxidation step using NH3 nitridation followed by re-oxidation
TAIWAN SEMICONDUCTOR MFG83 citations98
US6362085B1Mar 26, 2002
Method for reducing gate oxide effective thickness and leakage current
TAIWAN SEMICONDUCTOR MFG61 citations96
US6171911B1Jan 9, 2001
Method for forming dual gate oxides on integrated circuits with advanced logic devices
TAIWAN SEMICONDUCTOR MFG57 citations96
US6689665B1Feb 10, 2004
Method of forming an STI feature while avoiding or reducing divot formation
TAIWAN SEMICONDUCTOR MFG28 citations93
US6624090B1Sep 23, 2003
Method of forming plasma nitrided gate dielectric layers
TAIWAN SEMICONDUCTOR MFG38 citations93
US6566205B1May 20, 2003
Method to neutralize fixed charges in high K dielectric
TAIWAN SEMICONDUCTOR MFG41 citations93
US6465323B1Oct 15, 2002
Method for forming semiconductor integrated circuit microelectronic fabrication having multiple gate dielectric layers with multiple thicknesses
TAIWAN SEMICONDUCTOR MFG25 citations93
US6319784B1Nov 20, 2001
Using high temperature H2 anneal to recrystallize S/D and remove native oxide simultaneously
TAIWAN SEMICONDUCTOR MFG48 citations93
US6204205B1Mar 20, 2001
Using H2anneal to improve the electrical characteristics of gate oxide
TAIWAN SEMICONDUCTOR MFG42 citations93
US6184155B1Feb 6, 2001
Method for forming a ultra-thin gate insulator layer
TAIWAN SEMICONDUCTOR MFG39 citations93
US6180543B1Jan 30, 2001
Method of generating two nitrogen concentration peak profiles in gate oxide
TAIWAN SEMICONDUCTOR MFG27 citations93
US7118974B2Oct 10, 2006
Method of generating multiple oxides by plasma nitridation on oxide
TAIWAN SEMICONDUCTOR MFG22 citations92
US6825133B2Nov 30, 2004
Use of fluorine implantation to form a charge balanced nitrided gate dielectric layer
TAIWAN SEMICONDUCTOR MFG27 citations92
US6818553B1Nov 16, 2004
Etching process for high-k gate dielectrics
TAIWAN SEMICONDUCTOR MFG27 citations92
US6767847B1Jul 27, 2004
Method of forming a silicon nitride-silicon dioxide gate stack
TAIWAN SEMICONDUCTOR MFG37 citations92
US6759302B1Jul 6, 2004
Method of generating multiple oxides by plasma nitridation on oxide
TAIWAN SEMICONDUCTOR MFG35 citations92
US6380104B1Apr 30, 2002
Method for forming composite gate dielectric layer equivalent to silicon oxide gate dielectric layer
TAIWAN SEMICONDUCTOR MFG45 citations92
US6323143B1Nov 27, 2001
Method for making silicon nitride-oxide ultra-thin gate insulating layers for submicrometer field effect transistors
TAIWAN SEMICONDUCTOR MFG40 citations92
US6573193B2Jun 3, 2003
Ozone-enhanced oxidation for high-k dielectric semiconductor devices
TAIWAN SEMICONDUCTOR MFG34 citations91
US6110780AAug 29, 2000
Using NO or N2 O treatment to generate different oxide thicknesses in one oxidation step for single poly non-volatile memory
TAIWAN SEMICONDUCTOR MFG31 citations90
US7138317B2Nov 21, 2006
Method of generating multiple oxides by plasma nitridation on oxide
TAIWAN SEMICONDUCTOR MFG9 citations74
US6232241B1May 15, 2001
Pre-oxidation cleaning method for reducing leakage current of ultra-thin gate oxide
TAIWAN SEMICONDUCTOR MFG12 citations74
US6764959B2Jul 20, 2004
Thermal compensation method for forming semiconductor integrated circuit microelectronic fabrication
TAIWAN SEMICONDUCTOR MFG5 citations63
US6649535B1Nov 18, 2003
Method for ultra-thin gate oxide growth
TAIWAN SEMICONDUCTOR MFG4 citations63