Method for making FET gate oxides with different thicknesses using a thin silicon nitride layer and a single oxidation step

Abstract

A method for making a dual-gate oxide field effect transistors is achieved. The method utilizes a patterned thin silicon nitride layer and a single rapid thermal oxidation step to form a thicker gate oxide for memory and peripheral circuits while forming a thin nitrogen rich gate oxide for high-performance logic circuits. After forming STI around the logic and memory call areas and removing any native oxide, a thin CVD silicon nitride layer is deposited. The Si 3 N 4 is patterned to leave portions over the logic device areas. A single rapid thermal oxidation process is performed to grow a thicker gate oxide on the exposed memory areas while concurrently the Si 3 N 4 is slowly converted to a nitrogen-rich oxide and forms a thinner gate oxide on the logic device areas. The thinner nitrogen-rich gate oxide also retards boron diffusion to make more stable devices.

What is claimed is:  
     
       1. A method for fabricating dual gate oxides on the same integrated circuit chip comprising the steps of: 
       providing a semiconductor substrate having logic device areas and memory device areas surrounded and electrically isolated by field oxide regions;  
       removing a first native oxide from said logic and memory device areas;  
       depositing a blanket silicon nitride (Si 3 N 4 ) layer on said substrate;  
       patterning said Si 3 N 4  layer leaving portions over said logic device areas and exposing surface of said memory device areas;  
       removing a second native oxide from said memory device areas;  
       oxidizing surface of said substrate to form a gate oxide on said memory device areas and concurrently to convert said Si 3 N 4  layer to a nitrogen-rich silicon oxide layer on said logic device areas;  
       depositing and patterning a polysilicon layer to form FET gate electrodes.  
     
     
       2. The method of  claim 1 , wherein said semiconductor substrate is single crystal silicon. 
     
     
       3. The method of  claim 1 , wherein said first and second native oxides are removed in a hydrofluoric acid solution. 
     
     
       4. The method of  claim 1 , wherein said silicon nitride is deposited by chemical vapor deposition using dichlorosilane and ammonia. 
     
     
       5. The method of  claim 1 , wherein said silicon nitride is deposited to a thickness of between about 10 and 20 Angstroms. 
     
     
       6. The method of  claim 1 , wherein said silicon nitride layer is patterned using a photoresist mask and a wet etch in a heated phosphoric acid (H 3 PO 4 ) solution at a temperature of between about 100 and 200° C. 
     
     
       7. The method of  claim 1 , wherein said oxidizing of said surface is carried out using rapid thermal processing in steam at a temperature of at least 900° C. 
     
     
       8. The method of  claim 1 , wherein said gate oxide on said memory device areas is grown to a thickness of at least 50 Angstroms, while concurrently oxidizing said silicon nitride layer over said logic device areas to form said nitrogen-rich silicon oxide to a thickness of less than 25 Angstroms while completing said oxidation to said substrate surface. 
     
     
       9. The method of  claim 1 , wherein said polysilicon layer is conductively doped and is patterned by using a photoresist mask and plasma etching. 
     
     
       10. The method of  claim 1 , wherein said polysilicon layer includes an upper metal silicide layer to improve electrical conductivity. 
     
     
       11. A method for fabricating dual gate oxides on the same integrated circuit chip comprising steps of: 
       providing a single-crystal silicon semiconductor substrate having logic device areas and memory device areas surrounded and electrically isolated by field oxide regions;  
       removing a first native oxide from said logic and memory device areas;  
       depositing a blanket silicon nitride (Si 3 N 4 ) layer on said substrate;  
       patterning said Si 3 N 4  layer leaving portions over said logic device areas and exposing surface of said memory device areas;  
       removing a second native oxide from said memory device areas;  
       oxidizing surface of said substrate rapid thermal processing and forming a gate oxide on said memory device areas and concurrently converting said Si 3 N 4  layer to a nitrogen-rich silicon oxide layer on said logic device areas;  
       depositing and patterning a polysilicon layer to form FET gate electrodes.  
     
     
       12. The method of  claim 11 , wherein said first and second native oxides are removed in a hydrofluoric acid solution. 
     
     
       13. The method of  claim 11 , wherein said silicon nitride is deposited by chemical vapor deposition using dichlorosilane and ammonia. 
     
     
       14. The method of  claim 11 , wherein said silicon nitride is deposited to a thickness of between about 10 and 20 Angstroms. 
     
     
       15. The method of  claim 11 , wherein said silicon nitride layer is patterned using a photoresist mask and a wet etch in a heated phosphoric acid (H 3 PO 4 ) solution at a temperature of between about 100 and 200° C. 
     
     
       16. The method of  claim 11 , wherein said rapid thermal processing is carried out using steam at a temperature of at least 900° C. 
     
     
       17. The method of  claim 11 , wherein said gate oxide on said memory device areas is grown to a thickness of at least 50 Angstroms, while concurrently oxidizing said silicon nitride layer over said logic device areas to form said nitrogen-rich silicon oxide to a thickness of less than 25 Angstroms while completing said oxidation to said substrate surface. 
     
     
       18. The method of  claim 11 , wherein said polysilicon layer is conductively doped and is patterned by using a photoresist mask and plasma etching. 
     
     
       19. The method of  claim 1 , wherein said polysilicon layer includes an upper metal silicide layer to improve electrical conductivity.