Inventor

ARSOVSKI IGOR

US108 patents

⚠️ This page may combine multiple inventors who share the name “ARSOVSKI IGOR”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

ARSOVSKI IGOR

IBM

Static random access memory (SRAM) write assist circuit with leakage suppression and level control

Implementing computational memory from content-addressable memory

Apparatus and method for implementing memory array device with built in computational capability

Low power, single-ended sensing in a multi-port SRAM using pre-discharged bit lines

Content addressable memory with concurrent two-dimensional search capability in both row and column directions

Design structures, method and systems of powering on integrated circuit

Apparatus and method for low power, single-ended sensing in a multi-port SRAM using pre-discharged bit lines

Single ended sensing circuits for signal lines

Learning artificial neural network using ternary content addressable memory (TCAM)

Majority dominant power scheme for repeated structures and structures thereof

Apparatus and method for implementing matrix-based search capability in content addressable memory devices

Self-referenced match-line sense amplifier for content addressable memories

Design structures of powering on integrated circuit

Device and method to eliminate step response power supply perturbation

Design structure for a flexible multimode logic element for use in a configurable mixed-logic signal distribution path

Flexible multimode logic element for use in a configurable mixed-logic signal distribution path

Flexible multimode logic element for use in a configurable mixed-logic signal distribution path

Method for low power sensing in a multi-port SRAM using pre-discharged bit lines

Transition balancing for noise reduction/Di/Dt reduction during design, synthesis, and physical design

Transition balancing for noise reduction /Di/Dt reduction during design, synthesis, and physical design

CAM asynchronous search-line switching

Customer-transparent logic redundancy for improved yield

CAM asynchronous search-line switching

Design structure for a flexible multimode logic element for use in a configurable mixed-logic signal distribution path

Self-referenced match-line sense amplifier for content addressable memories

Ternary content addressable memory

TCAM structures with reduced power supply noise

Composite views for IP blocks in ASIC designs

Converting an XY TCAM to a value TCAM

High density search engine

Customer-transparent logic redundancy for improved yield

ARSOVSKI IGOR

Structure for implementing memory array device with built in computation capability

Environmental and computing cost reduction with improved reliability in workload assignment to distributed computing nodes

Majority dominant power scheme for repeated structures and structures thereof

SRAM having wordline up-level voltage adjustable to assist bitcell stability and design structure for same

Method and apparatus for configuring a content-addressable memory (CAM) design as binary CAM or ternary CAM

Adaptive noise suppression using a noise look-up table

SRAM delay circuit that tracks bitcell characteristics

Content addressable memory with concurrent read and search/compare operations at the same memory cell

Circuit structure and method for digital integrated circuit performance screening

GLOBALFOUNDRIES INC

Bias temperature instability state detection and correction

Self pre-charging memory circuits

Content-addressable memory having multiple reference matchlines to reduce latency

Matchline precharge architecture for self-reference matchline sensing

Bending circuit for static random access memory (SRAM) self-timer

MOSAID TECHNOLOGIES INC

Mismatch-dependent power allocation technique for match-line sensing in content-addressable memories

Low power match-line sensing circuit

Low power match-line sensing circuit

Mismatch-dependent power allocation technique for match-line sensing in content-addressable memories

MARVELL INT LTD

Multiple sense amplifier and data path-based pseudo dual port SRAM