SRAM having wordline up-level voltage adjustable to assist bitcell stability and design structure for same

Abstract

An integrated circuit that includes memory containing wordlines and bitcells having SRAM storage elements and being connected to the wordlines. Wordline up-level assist circuitry is provided that is designed and configured to provide a plurality of selectable voltage values that can be selected to provide the wordline up-level voltage that is provided to the bitcells during a memory read cycle and/or write cycle. In one example, the voltage value selected is selected based on characterization of the as-fabricated bitcells so as to decrease the likelihood of the bitcells experiencing a stability failure.

1. An integrated circuit, comprising:
 a memory array comprising a plurality of bitcells having a static-random-access-memory (SRAM) architecture; 
 a plurality of wordlines operatively connected to said plurality of bitcells; and 
 wordline driver circuitry designed and configured to provide a wordline up-level voltage to each of said plurality of wordlines, said wordline driver circuitry including wordline up-level assist circuitry designed and configured to provide a plurality of selectable values for the wordline up-level voltage; 
 wherein:
 said wordline up-level assist circuitry includes at least one pull-down device operatively coupled to at least one of said plurality of wordlines so that when said at least one pull-down device is activated, said at least one pull-down device pulls the wordline up-level voltage to one of said plurality of selectable values; 
 said wordline up-level assist circuitry includes first and second pull-down devices operatively coupled to at least one of said plurality of wordlines and being independently selectable so as to provide multiple ones of said plurality of selectable values; and 
 said first pull-down device has a pull-down strength and said second pull-down device has a pull-down strength that is about twice said pull-down strength of said first pull-down device. 
 
 
     
     
       2. An integrated circuit according to  claim 1 , wherein said at least one pull-down device is a transistor. 
     
     
       3. An integrated circuit according to  claim 1 , wherein said at least one pull-down device is responsive to a gate voltage and said wordline up-level assist circuitry includes circuitry designed and configured to provide a plurality of values of the gate voltage so as to provide corresponding ones of said plurality of selectable values. 
     
     
       4. An integrated circuit according to  claim 1 , wherein said wordline up-level assist circuitry includes at least one pull-down device for each of said plurality of wordlines. 
     
     
       5. An integrated circuit according to  claim 1 , wherein each of said at least one pull-down device is electrically coupled to multiple ones of said plurality of wordlines. 
     
     
       6. An integrated circuit according to  claim 1 , wherein said wordline up-level assist circuitry is designed and configured to be active only during a read cycle of said memory array. 
     
     
       7. An integrated circuit according to  claim 1 , further comprising wordline pulse circuitry and delay circuitry in electrical communication with said wordline pulse circuitry, said delay circuitry including:
 a plurality of cells having said SRAM architecture; and 
 a delay buffer grounded through said plurality of cells; 
 wherein said plurality of cells are driven by said wordline up-level assist circuitry. 
 
     
     
       8. An integrated circuit according to  claim 1 , wherein said wordline driver circuitry includes wordline pulse circuitry and said SRAM circuitry further includes delay circuitry in electrical communication with said wordline pulse circuitry, said delay circuitry including:
 a plurality of cells having SRAM architecture; and 
 a delay buffer grounded through said plurality of cells; 
 wherein said plurality of cells are driven by said wordline up-level assist circuitry. 
 
     
     
       9. An integrated circuit, comprising:
 static random access memory (SRAM) circuitry that includes:
 a complementary pair of bitlines having a first bitline and a second bitline; 
 a first pass-gate device having a first gate electrode; 
 a second pass-gate device having a second gate electrode; 
 a bit cell containing:
 a first internal node electrically coupled to said first bitline across said first pass-gate device, said first internal node provided to be charged to a bit-value voltage level during use of said bit cell to store a bit value; and 
 a second internal node electrically coupled to said second bitline across said second pass-gate device, said second internal node provided to be charged to the complement of the bit value voltage level during use of said bit cell to store the bit value; 
 
 a wordline electrically coupled to each of said first and second gate electrodes, respectively, of said first and second pass-gate transistors; and 
 wordline driver circuitry electrically coupled to said wordline so as to provide said wordline with an up-level voltage, wherein said wordline driver circuitry includes:
 wordline up-level assist circuitry configured to provide, one at a time, a plurality of selectable predetermined voltage levels for the up-level voltage; and 
 selection circuitry responsive to a selection input that effects the selection of the up-level voltage from the plurality of selectable predetermined voltage values; 
 
 wherein: 
 said wordline driver circuitry further includes a voltage source operatively configured to drive said wordline with an up-level pulse in response to a memory-operation event, said wordline up-level assist circuitry including at least one pull-down device each electrically coupled to said input circuitry and to said wordline downstream of said voltage source and upstream of said first and second pass-gate devices in a manner that provides the ability to pull-down the wordline up-level voltage of the wordline to one of the plurality of selectable predetermined voltage values in response to the selection input; and 
 said at least one pull-down device includes a first pull-down device having a first current strength and a second pull-down device having a second current strength that is about twice said second current strength, wherein each of said first and second pull-down devices are independently controllable so as to provide four possible predetermined up-level voltages. 
 
 
     
     
       10. An integrated circuit according to  claim 9 , wherein said at least one pull-down device is responsive to a gate voltage and said wordline up-level assist circuitry includes circuitry designed and configured to provide a plurality of values of the gate voltage so as to provide corresponding ones of said plurality of selectable values. 
     
     
       11. An integrated circuit according to  claim 9 , wherein said wordline up-level assist circuitry is designed and configured to be active only during a read cycle of said SRAM circuitry. 
     
     
       12. An integrated circuit, comprising:
 a memory array comprising a plurality of bitcells having a static-random-access-memory (SRAM) architecture; 
 a plurality of wordlines operatively connected to said plurality of bitcells; 
 wordline driver circuitry designed and configured to provide a wordline up-level voltage to each of said plurality of wordlines, said wordline driver circuitry including wordline up-level assist circuitry designed and configured to provide a plurality of selectable values for the wordline up-level voltage; and 
 wordline pulse circuitry and delay circuitry in electrical communication with said wordline pulse circuitry, said delay circuitry including:
 a plurality of cells having said SRAM architecture; and 
 a delay buffer grounded through said plurality of cells; 
 wherein said plurality of cells are driven by said wordline up-level assist circuitry. 
 
 
     
     
       13. An integrated circuit according to  claim 12 , wherein said wordline up-level assist circuitry includes at least one pull-down device operatively coupled to at least one of said plurality of wordlines so that when said at least one pull-down device is activated, said at least one pull-down device pulls the wordline up-level voltage to one of said plurality of selectable values. 
     
     
       14. An integrated circuit according to  claim 13 , wherein said wordline up-level assist circuitry includes first and second pull-down devices operatively coupled to at least one of said plurality of wordlines and being independently selectable so as to provide multiple ones of said plurality of selectable values. 
     
     
       15. An integrated circuit according to  claim 14 , wherein said first pull-down device has a pull-down strength and said second pull-down device has a pull-down strength that is about twice said pull-down strength of said first pull-down device. 
     
     
       16. An integrated circuit according to  claim 13 , wherein said at least one pull-down device is a transistor. 
     
     
       17. An integrated circuit according to  claim 13 , wherein said at least one pull-down device is responsive to a gate voltage and said wordline up-level assist circuitry includes circuitry designed and configured to provide a plurality of values of the gate voltage so as to provide corresponding ones of said plurality of selectable values. 
     
     
       18. An integrated circuit according to  claim 13 , wherein said wordline up-level assist circuitry includes at least one pull-down device for each of said plurality of wordlines. 
     
     
       19. An integrated circuit according to  claim 13 , wherein each of said at least one pull-down device is electrically coupled to multiple ones of said plurality of wordlines. 
     
     
       20. An integrated circuit according to  claim 12 , wherein said wordline up-level assist circuitry is designed and configured to be active only during a read cycle of said memory array. 
     
     
       21. An integrated circuit, comprising:
 static random access memory (SRAM) circuitry that includes:
 a complementary pair of bitlines having a first bitline and a second bitline; 
 a first pass-gate device having a first gate electrode; 
 a second pass-gate device having a second gate electrode; 
 a bit cell containing:
 a first internal node electrically coupled to said first bitline across said first pass-gate device, said first internal node provided to be charged to a bit-value voltage level during use of said bit cell to store a bit value; and 
 a second internal node electrically coupled to said second bitline across said second pass-gate device, said second internal node provided to be charged to the complement of the bit value voltage level during use of said bit cell to store the bit value; 
 
 a wordline electrically coupled to each of said first and second gate electrodes, respectively, of said first and second pass-gate transistors; and 
 wordline driver circuitry electrically coupled to said wordline so as to provide said wordline with an up-level voltage, wherein said wordline driver circuitry includes:
 wordline up-level assist circuitry configured to provide, one at a time, a plurality of selectable predetermined voltage levels for the up-level voltage; and 
 selection circuitry responsive to a selection input that effects the selection of the up-level voltage from the plurality of selectable predetermined voltage values; 
 
 wherein said wordline driver circuitry includes wordline pulse circuitry and said SRAM circuitry further includes delay circuitry in electrical communication with said wordline pulse circuitry, said delay circuitry including:
 a plurality of cells having SRAM architecture; and 
 a delay buffer grounded through said plurality of cells; 
 wherein said plurality of cells are driven by said wordline up-level assist circuitry. 
 
 
 
     
     
       22. An integrated circuit according to  claim 21 , wherein said wordline driver circuitry further includes a voltage source operatively configured to drive said wordline with an up-level pulse in response to a memory-operation event, said wordline up-level assist circuitry including at least one pull-down device each electrically coupled to said input circuitry and to said wordline downstream of said voltage source and upstream of said first and second pass-gate devices in a manner that provides the ability to pull-down the wordline up-level voltage of the wordline to one of the plurality of selectable predetermined voltage values in response to the selection input. 
     
     
       23. An integrated circuit according to  claim 22 , wherein said at least one pull-down device includes a first pull-down device having a first current strength and a second pull-down device having a second current strength that is about twice said second current strength, wherein each of said first and second pull-down devices are independently controllable so as to provide four possible predetermined up-level voltages. 
     
     
       24. An integrated circuit according to  claim 21 , wherein said at least one pull-down device is responsive to a gate voltage and said wordline up-level assist circuitry includes circuitry designed and configured to provide a plurality of values of the gate voltage so as to provide corresponding ones of said plurality of selectable values. 
     
     
       25. An integrated circuit according to  claim 21 , wherein said wordline up-level assist circuitry is designed and configured to be active only during a read cycle of said SRAM.