Inventor

PILO HAROLD

US101 patents

⚠️ This page may combine multiple inventors who share the name “PILO HAROLD”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

PILO HAROLD

IBM

Programmable impedance output driver

Memory having user programmable AC timings

Variable impedance output driver circuit using analog biases to match driver output impedance to load input impedance

Cycle independent data to echo clock tracking circuit

Static random access memory (SRAM) write assist circuit with leakage suppression and level control

Semiconductor memory device having resistive bitline contact testing

Structure for power-efficient cache memory

Adaptive integrated circuit based on transistor current measurements

Reduced latency wide-I/O burst architecture

System and method for early write to memory by holding bitline at fixed potential

Overvoltage protection for a fine grained negative wordline scheme

Apparatus and method for small signal sensing in an SRAM cell utilizing PFET access devices

System and method for integrating dynamic leakage reduction with write-assisted SRAM architecture

BIST circuit for variable impedance system

Efficient semiconductor burn-in circuit and method of operation

Computer unit responsive to difference between external clock period and circuit characteristic period

SRAM write-assisted operation with VDD-to-VCS level shifting

Leakage compensated reference voltage generation system

Column selectable self-biasing virtual voltages for SRAM write assist

Low overhead switched header power savings apparatus

Voltage controlled static random access memory

Apparatus and method for small signal sensing in an SRAM cell utilizing PFET access devices

Delay-lock-loop with improved accuracy and range

System and method for implementing a micro-stepping delay chain for a delay locked loop

Method and apparatus for improving cycle time in a quad data rate SRAM device

Special mode enable transparent to normal mode operation

Overvoltage protection for a fine grained negative wordline scheme

Overvoltage protection for a fine grained negative wordline scheme

Overvoltage protection for a fine grained negative wordline scheme

Leakage-aware voltage regulation circuit and method

Duty-cycle-efficient SRAM cell test

Sense-amplifier assist (SAA) with power-reduction technique

Scalable termination

Current control mechanism for dynamic logic keeper circuits in an integrated circuit and method of regulating same

Voltage controlled static random access memory

Adaptive integrated circuit based on transistor current measurements

System and method for implementing a micro-stepping delay chain for a delay locked loop

Method and circuit for precise timing of signals in an embedded DRAM array

System and method for testing a column redundancy of an integrated circuit memory

System and method for early write to memory by injecting small voltage signal

Alternating reference wordline scheme for fast DRAM

ADAMS CHAD A

Apparatus and method for implementing write assist for static random access memory arrays

Single supply sub VDD bit-line precharge SRAM and method for level shifting

ARSOVSKI IGOR

SRAM having wordline up-level voltage adjustable to assist bitcell stability and design structure for same

SRAM delay circuit that tracks bitcell characteristics

MOTOROLA INC

Memory having a latching BICMOS sense amplifier

GLOBALFOUNDRIES INC

SRAM circuit with increased write margin

SYNOPSYS INC

Memory bypass function for a memory

INVECAS INC

Deep-sleep wake up for a memory device

BRACERAS GEORGE M

Dual power supply memory array having a control circuit that dynamically selects a lower of two supply voltages for bitline pre-charge operations and an associated method