Inventor

BANGSARUNTIP SARUNYA

US74 patents

⚠️ This page may combine multiple inventors who share the name “BANGSARUNTIP SARUNYA”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

BANGSARUNTIP SARUNYA

BANGSARUNTIP SARUNYA

Epitaxially thickened doped or undoped core nanowire FET structure and method for increasing effective device width

Replacement gate fin first wire last gate all around devices

Nanowire FET and finFET hybrid technology

Process for forming a surrounding gate for a nanowire using a sacrificial patternable dielectric

Contacts for nanowire field effect transistors

Hybrid CMOS technology with nanowire devices and double gated planar devices

Planar and nanowire field effect transistors

Maskless process for suspending and thinning nanowires

Generation of multiple diameter nanowire field effect transistors

Nanowire tunnel field effect transistors

Nanowire circuits in matched devices

Gate-all-around nanowire tunnel field effect transistors

Self-aligned contacts for nanowire field effect transistors

Nanowire field effect transistor device

Hybrid CMOS technology with nanowire devices and double gated planar devices

Nanowire field effect transistor device

Nanowire FET having induced radial strain

Nanowire field effect transistors

Generation of multiple diameter nanowire field effect transistors

Nanowire FET having induced radial strain

Nanowire FET having induced radial strain

MOSFET with a nanowire channel and fully silicided (FUSI) wrapped around gate

Omega shaped nanowire tunnel field effect transistors fabrication

Omega shaped nanowire field effect transistors

Nanowire pin tunnel field effect devices

MOSFET with a nanowire channel and fully silicided (FUSI) wrapped around gate

Nanowire field effect transistors

Nanowire field effect transistors

Generation of multiple diameter nanowire field effect transistors

Nanowire floating gate transistor

Planar and nanowire field effect transistors

IBM

Nanowire field-effect transistors

Maskless process for suspending and thinning nanowires

Gate-all-around nanowire field effect transistors

Nanowire capacitor for bidirectional operation

Nanowire FET and FinFET hybrid technology

Different thickness oxide silicon nanowire field effect transistors

Gate patterning of nano-channel devices

Fabrication of nanomaterial T-gate transistors with charge transfer doping layer

Fabrication of nanomaterial T-gate transistors with charge transfer doping layer

Nanowire capacitor for bidirectional operation

Metal surface protection

Superconductor devices having buried quasiparticle traps

Tapered nanowire structure with reduced off current

SLEIGHT JEFFREY W

Nanowire FET with trapezoid gate structure

Two-step hydrogen annealing process for creating uniform non-planar semiconductor devices at aggressive pitch

Nanowire FET with trapezoid gate structure

INTERNAT BUSINESS MACHIENS COR

Techniques for fabricating nanowire field-effect transistors

SCHROTT ALEJANDRO G

Nanoscale electrodes for phase change memory devices

GLOBALFOUNDRIES INC

Process for forming a surrounding gate for a nanowire using a sacrificial patternable dielectric