Inventor

MAKARAM RAGHUNANDAN

US70 patents

⚠️ This page may combine multiple inventors who share the name “MAKARAM RAGHUNANDAN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

MAKARAM RAGHUNANDAN

INTEL CORP

Using authenticated manifests to enable external certification of multi-processor platforms

Supporting secure memory intent

Flexible architecture and instruction for advanced encryption standard (AES)

Configuring power management functionality in a processor

Protect non-memory encryption engine (non-mee) metadata in trusted execution environment

Supporting secure memory intent

Secure memory repartitioning

Composable trustworthy execution environments

Host-convertible secure enclaves in memory that leverage multi-key total memory encryption with integrity

Supporting secure memory intent

Supporting configurable security levels for memory address ranges

Supporting configurable security levels for memory address ranges

Method to increase cloud availability and silicon isolation using secure enclaves

Process-based multi-key total memory encryption

Secure stream protocol for serial interconnect

System, apparatus and method for providing protection against silent data corruption in a link

Secure stream protocol for serial interconnect

Flexible architecture and instruction for advanced encryption standard (AES)

Flexible architecture and instruction for advanced encryption standard (AES)

Flexible architecture and instruction for advanced encryption standard (AES)

Flexible architecture and instruction for advanced encryption standard (AES)

Flexible architecture and instruction for advanced encryption standard (AES)

Flexible architecture and instruction for advanced encryption standard (AES)

Flexible architecture and instruction for advanced encryption standard (AES)

Flexible architecture and instruction for advanced encryption standard (AES)

Flexible architecture and instruction for advanced encryption standard (AES)

Flexible architecture and instruction for advanced encryption standard (AES)

Flexible architecture and instruction for advanced encryption standard (AES)

Flexible architecture and instruction for advanced encryption standard (AES)

Flexible architecture and instruction for advanced encryption standard (AES)

Flexible architecture and instruction for advanced encryption standard (AES)

Flexible architecture and instruction for advanced encryption standard (AES)

Flexible architecture and instruction for advanced encryption standard (AES)

Flexible architecture and instruction for advanced encryption standard (AES)

Flexible architecture and instruction for advanced encryption standard (AES)

Flexible architecture and instruction for advanced encryption standard (AES)

Flexible architecture and instruction for advanced encryption standard (AES)

Flexible architecture and instruction for advanced encryption standard (AES)

Composable trusted execution environments

Methods, apparatus, and instructions for user-level thread suspension

Supporting secure memory intent

Data release control based on authentication and link protection

Securing platform link with encryption

Ultra-secure accelerators

Supporting secure memory intent

Data release control based on authentication and link protection

Multicore processor with a control register storing an indicator that two or more cores are to operate at independent performance states

TAHOE RES LTD

Process-based multi-key total memory encryption

Process-based multi-key total memory encryption

BHANDARU MALINI K

Configuring power management functionality in a processor including a plurality of cores by utilizing a register to store a power domain indicator