Inventor

CHIANG TING-WEI

TW164 patents

⚠️ This page may combine multiple inventors who share the name “CHIANG TING-WEI”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

CHIANG TING-WEI

TAIWAN SEMICONDUCTOR MFG CO LTD

Flip-flop with delineated layout for reduced footprint

Integrated circuit and method of forming an integrated circuit

Integrated circuit and method of forming an integrated circuit

System and method of processing cutting layout and example switching circuit

Transmission gate structure and method

Power rail with non-linear edge

Method of designing an integrated circuit and integrated circuit

Buried metal track and methods forming same

Integrated circuit layout method, device, and system

Double height cell regions, semiconductor device having the same, and method of generating a layout diagram corresponding to the same

Integrated circuit, system for and method of forming an integrated circuit

Integrated circuit and method of manufacturing same

Semiconductor device having engineering change order (ECO) cells and method of using

Flip-flop with delineated layout for reduced footprint

Buried metal track and methods forming same

Layout of standard cells for predetermined function in integrated circuits

Method of generating engineering change order (ECO) layout of base cell and computer-readable medium comprising executable instructions for carrying out said method

Flip-flop with delineated layout for reduced footprint

Method of forming layout design

FinFET with an asymmetric source/drain structure and method of making same

Connecting techniques for stacked CMOS devices

System and method of layout design for integrated circuits

Standard cell having cell height being non-integral multiple of nominal minimum pitch

Method and system of layout placement based on multilayer gridlines

Standard cells for predetermined function having different types of layout

Connecting techniques for stacked CMOS devices

Semiconductor device and method of manufacturing semiconductor device

Semiconductor structure

Method of modifying cell and global connection routing method

Circuits and structures including tap cells and fabrication methods thereof

Tie off device

Power rail with non-linear edge

Integrated circuit structure

Double height cell regions, semiconductor device having the same, and method of generating a layout diagram corresponding to the same

Pin modification for standard cells

Integrated circuit having angled conductive feature

Integrated circuit layout method and system

Integrated circuit layout and method of configuring the same

Semiconductor device including power-grid-adapted route-spacing and method for generating layout diagram of same

Semiconductor device and layout design thereof

Pin modification for standard cells

Transmission gate structure, layout, methods, and system

Integrated circuit, system for and method of forming an integrated circuit

Pin modification for standard cells

System and method of processing cutting layout and example switching circuit

Connecting techniques for stacked CMOS devices

System for designing integrated circuit layout and method of making the integrated circuit layout

TAIWAN SEMICONDUCTOR MFG

Method of forming layout design

FinFET with an asymmetric source/drain structure and method of making same

Standard cell metal structure directly over polysilicon structure