Double height cell regions, semiconductor device having the same, and method of generating a layout diagram corresponding to the same
Abstract
In at least one cell region, a semiconductor device includes fin patterns and at least one overlying gate structure. The fin patterns (dummy and active) are substantially parallel to a first direction. Each gate structure is substantially parallel to a second direction (which is substantially perpendicular to the first direction). First and second active fin patterns have corresponding first and second conductivity types. Each cell region, relative to the second direction, includes: a first active region which includes a sequence of three or more consecutive first active fin patterns located in a central portion of the cell region; a second active region which includes one or more second active fin patterns located between the first active region and a first edge of the cell region; and a third active region which includes one or more second active fin patterns located between the first active region and a second edge of the cell region.
Claims
exact text as granted — not AI-modifiedWhat is claimed is:
1. A method of generating a layout diagram, the layout diagram being stored on a non-transitory computer-readable medium, the method comprising:
selecting a standard cell from a library; and
including the standard cell in a layout diagram; and
wherein:
the standard cell includes:
fin patterns arranged substantially parallel to a first direction, the fin patterns including:
dummy fin patterns;
first active fin patterns of a first conductivity type; and
second active fin patterns of a second conductivity type; and
at least one gate pattern arranged substantially parallel to a second direction which is substantially perpendicular to the first direction, the at least one gate pattern being further arranged over corresponding ones of the fin patterns;
the standard cell is arranged to include first, second and third active regions such that:
the first active region, which includes a sequence of three or more consecutive first active fin patterns, is located in a central portion of the standard cell;
the second active region, which includes one or more second active fin patterns, is located between the first active region and a first edge of the standard cell; and
the third active region, which includes one or more second active fin patterns, is located between the first active region and a second edge of the standard cell; and
at least one aspect of the method is executed by a processor of a computer; and
based on the layout diagram, at least one of (A) making one or more photolithographic exposures, or (B) fabricating one or more semiconductor masks, or (C) fabricating at least one component in a layer of a semiconductor integrated circuit.
2. The method of claim 1 , wherein:
a first one of the dummy fin patterns is located, relative to the second direction, between the second active region and a first edge of a cell region; and
a second one of the dummy fin patterns is located, relative to the second direction, between the third active region and a second edge of the cell region.
3. The method of claim 2 , wherein:
the first edge of the cell region, relative to the first direction, is substantially collinear with a long axis of the first one of the dummy fin patterns; and
the second edge of the cell region, relative to the first direction, is substantially collinear with a long axis of the second one of the dummy fin patterns.
4. The method of claim 2 , wherein the cell region is a double height cell region.
5. The method of claim 1 , wherein a sum of the second active fin patterns in the second active region equals a sum of the second active fin patterns in the third active region.
6. The method of claim 1 , wherein a sum of the second active fin patterns in the second active region is less than a sum of the second active fin patterns in the third active region.
7. The method of claim 1 , wherein:
the fin patterns and at least one gate structure are located in at least two cell regions; and
each of the at least two cell regions includes:
at least three gate structures, at least one of which is a dummy gate structure and at least one of which is an active gate structure; and
a boundary, relative to the first direction, between first and second ones of the at least two cell regions is defined by a consecutive sequence of a first active gate structure, a first dummy gate structure, a second dummy gate structure and a second active gate structure.
8. The method of claim 1 , wherein:
the fin patterns and at least one gate structure are located in at least two cell regions; and
each of the at least two cell regions includes:
at least three gate structures, at least one of which is a dummy gate structure and at least one of which is an active gate structure; and
a boundary, relative to the first direction, between first and second ones of the at least two cell regions is defined by a consecutive sequence of a first active gate structure, a first dummy gate structure and a second active gate structure.
9. The method of claim 1 , wherein:
a distance between immediately adjacent pairs of fin patterns is a fin pitch, the fin pitch being substantially uniform;
sizes, in the second direction, of the first active region, second active region and third active region are correspondingly based on the fin pitch; and
sizes, in the second direction, of a first gap between the first active region and the second active region and a second gap between the first active region and the third active region are correspondingly based on the fin pitch.
10. The method of claim 1 , wherein:
a distance between immediately adjacent pairs of fin patterns is a fin pitch, the fin pitch being substantially uniform;
sizes, in the second direction, of the first active region, second active region and third active region are correspondingly based on the fin pitch; and
sizes, in the second direction, of a first gap between the first active region and the second active region and a second gap between the first active region and the third active region are not correspondingly based on the fin pitch.
11. A method of generating a layout diagram, the layout diagram being stored on a non-transitory computer-readable medium, the method comprising:
selecting a standard cell from a library; and
including the standard cell in a layout diagram; and
wherein:
the standard cell includes:
fin patterns extending substantially parallel to a first direction; and
gate structure patterns formed over corresponding ones of the fin patterns and extending substantially parallel to a second direction which is substantially perpendicular to the first direction, the gate structure patterns being configured to include:
dummy gate structure patterns; and
active gate structure patterns; and
wherein:
the fin patterns and the gate structure patterns are organized into cell regions; and
a boundary, relative to the first direction, between first and second one of the cell regions is defined by a consecutive sequence of a first active gate structure, a first dummy gate structure and a second active gate structure; and
the fin patterns are configured to include:
dummy fin patterns;
first active fin patterns having a first conductivity type; and
second active fin patterns having a second conductivity type; and
the fin patterns and the gate structure patterns are located in corresponding ones of the cell regions; and
each cell region, relative to the second direction, includes:
a first active region which includes a sequence of three or more consecutive first active fin patterns located in a central portion of the cell region;
a second active region which includes one or more second active fin patterns located between the first active region and a first edge of the cell region; and
a third active region which includes one or more second active fin patterns located between the first active region and a second edge of the cell region; and
based on the layout diagram, at least one of (A) making one or more photolithographic exposures, or (B) fabricating one or more semiconductor masks, or (C) fabricating at least one component in a layer of a semiconductor integrated circuit.
12. The method of claim 11 , wherein:
a first one of the dummy fin patterns is located, relative to the second direction, between the second active region and a first edge of the cell region; and
a second one of the dummy fin patterns is located, relative to the second direction, between the third active region and a second edge of the cell region.
13. The method of claim 11 , wherein:
a distance between immediately adjacent pairs of fin patterns is a fin pitch, the fin pitch being substantially uniform;
sizes, in the second direction, of the first active region, second active region and third active region are correspondingly based on the fin pitch; and
sizes, in the second direction, of a first gap between the first active region and the second active region and a second gap between the first active region and the third active region are correspondingly based on the fin pitch.
14. The method of claim 11 , wherein:
a distance between immediately adjacent pairs of fin patterns is a fin pitch, the fin pitch being substantially uniform;
sizes, in the second direction, of the first active region, second active region and third active region are correspondingly based on the fin pitch; and
sizes, in the second direction, of a first gap between the first active region and the second active region and a second gap between the first active region and the third active region are not correspondingly based on the fin pitch.
15. The method of claim 11 , wherein the dummy gate structure patterns are not configured for a particular conductivity.
16. A method of generating a layout diagram, the layout diagram being stored on a non-transitory computer-readable medium, the method comprising:
selecting a standard cell from a library; and
including the standard cell in a layout diagram; and
wherein:
fin patterns, extending substantially parallel to a first direction, configured to include:
dummy fin patterns;
first active fin patterns having a first conductivity type; and
second active fin patterns having a second conductivity type; and
at least one gate structure formed over corresponding ones of the fin patterns and extending substantially parallel to a second direction which is substantially perpendicular to the first direction; and
wherein:
the fin patterns and the at least one gate structure are located in at least one cell region; and
each cell region, relative to the second direction, including:
a first active region which includes a sequence of three or more consecutive first active fin patterns located in a central portion of the cell region;
a second active region which includes one or more second active fin patterns located between the first active region and a first edge of the cell region; and
a third active region which includes one or more second active fin patterns located between the first active region and a second edge of the cell region; and
wherein:
a first one of the dummy fin patterns is located, relative to the second direction, between the second active region and a first edge of the cell region; and
a second one of the dummy fin patterns is located, relative to the second direction, between the third active region and a second edge of the cell region; and
based on the layout diagram, at least one of (A) making one or more photolithographic exposures, or (B) fabricating one or more semiconductor masks, or (C) fabricating at least one component in a layer of a semiconductor integrated circuit.
17. The method of claim 16 , wherein:
the first edge of the cell region, relative to the first direction, is substantially collinear with a long axis of the first one of the dummy fin patterns; and
the second edge of the cell region, relative to the first direction, is substantially collinear with a long axis of the second one of the dummy fin patterns.
18. The method of claim 16 , wherein the cell region is a double height cell region.
19. The method of claim 16 , wherein a sum of the second active fin patterns in the second active region equals a sum of the second active fin patterns in the third active region.
20. The method of claim 16 , wherein a sum of the second active fin patterns in the second active region is less than a sum of the second active fin patterns in the third active region.Cited by (0)
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