Inventor · disambiguated record
Lee-Chung Lu
Also filed as: LU LEE-CHUNG
190 granted patents·38 pending applications·1,099 citations·filing 2000–2025
99Inventor score
Files withTAIWAN SEMICONDUCTOR MFG CO LTD158TAIWAN SEMICONDUCTOR MFG38LU LEE-CHUNG14CHEN HUANG-YU6HOU YUNG-CHIN3
Top patents by PatentIndex Score
228 records- 0199US9641161B1Flip-flop with delineated layout for reduced footprintTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2016·Granted May 2, 2017·33 cites·20 claims
- 0298US11063045B2Semiconductor device and method of manufacturing the sameTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2020·Granted Jul 13, 2021·5 cites·20 claims
- 0398US10998340B2Semiconductor device including standard cells having different cell heightTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2019·Granted May 4, 2021·14 cites·20 claims
- 0498US10867114B2Integrated circuit and method of forming an integrated circuitTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2019·Granted Dec 15, 2020·12 cites·20 claims
- 0598US10380315B2Integrated circuit and method of forming an integrated circuitTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2017·Granted Aug 13, 2019·23 cites·20 claims
- 0697US11756999B2Double height cell regions, semiconductor device having the same, and method of generating a layout diagram corresponding to the sameTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2021·Granted Sep 12, 2023·3 cites·20 claims
- 0797US11632102B2Low-power flip-flop architecture with high-speed transmission gatesTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2021·Granted Apr 18, 2023·5 cites·20 claims
- 0897US11050423B1Flip-flop device and method of operating flip-flop deviceTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2020·Granted Jun 29, 2021·4 cites·20 claims
- 0997US10270430B2Cell of transmission gate free circuit and integrated circuit and integrated circuit layout including the sameTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2017·Granted Apr 23, 2019·17 cites·20 claims
- 1097US8584052B2Cell layout for multiple patterning technologyCHEN HUANG-YU·Filed 2011·Granted Nov 12, 2013·26 cites·19 claims
- 1196US12074168B2Semiconductor device and method of manufacturing the sameTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2023·Granted Aug 27, 2024·2 cites·20 claims
- 1296US11854943B2Memory macro including through-silicon viaTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2023·Granted Dec 26, 2023·2 cites·20 claims
- 1396US11755813B2Integrated circuit structureTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2021·Granted Sep 12, 2023·2 cites·20 claims
- 1496US11574865B2Method of forming semiconductor device including deep viasTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2021·Granted Feb 7, 2023·2 cites·20 claims
- 1596US9123565B2Masks formed based on integrated circuit layout design having standard cell that includes extended active regionTAIWAN SEMICONDUCTOR MFG·Filed 2013·Granted Sep 1, 2015·27 cites·23 claims
- 1696US7958465B2Dummy pattern design for reducing device performance driftTAIWAN SEMICONDUCTOR MFG·Filed 2008·Granted Jun 7, 2011·118 cites·20 claims
- 1795US9584099B2Flip flop circuitTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2014·Granted Feb 28, 2017·11 cites·20 claims
- 1895US9317646B2Masks formed based on integrated circuit layout design having cell that includes extended active regionTAIWAN SEMICONDUCTOR MFG·Filed 2015·Granted Apr 19, 2016·13 cites·20 claims
- 1995US8775977B2Decomposition and marking of semiconductor device design layout in double patterning lithographyHSU CHIN-CHANG·Filed 2011·Granted Jul 8, 2014·13 cites·17 claims
- 2094US12081215B2Level shifter circuit and method of operating the sameTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2023·Granted Sep 3, 2024·2 cites·20 claims
- 2194US12047079B2Flip-flop circuit and methodTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2023·Granted Jul 23, 2024·2 cites·20 claims
- 2294US11562946B2Memory macro including through-silicon viaTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2021·Granted Jan 24, 2023·3 cites·20 claims
- 2394US11011545B2Semiconductor device including standard cellsTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2018·Granted May 18, 2021·7 cites·20 claims
- 2494US8327301B2Routing method for double patterning designCHENG YI-KAN·Filed 2009·Granted Dec 4, 2012·22 cites·28 claims
- 2594US8119310B1Mask-shift-aware RC extraction for double patterning designLU LEE-CHUNG·Filed 2010·Granted Feb 21, 2012·11 cites·20 claims
- 2693US11842946B2Semiconductor package having an encapsulant comprising conductive fillers and method of manufactureTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2021·Granted Dec 12, 2023·2 cites·20 claims
- 2793US11790148B2Integrated circuit and method of forming an integrated circuitTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2020·Granted Oct 17, 2023·2 cites·20 claims
- 2893US11030372B2Method for generating layout diagram including cell having pin patterns and semiconductor device based on sameTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2019·Granted Jun 8, 2021·6 cites·20 claims
- 2993US10971586B2Double height cell regions, semiconductor device having the same, and method of generating a layout diagram corresponding to the sameTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2018·Granted Apr 6, 2021·5 cites·20 claims
- 3093US10741540B2Integrated circuit layout method and deviceTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2018·Granted Aug 11, 2020·5 cites·20 claims
- 3193US9543193B2Non-hierarchical metal layers for integrated circuitsTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2015·Granted Jan 10, 2017·8 cites·20 claims
- 3293US8443306B1Planar compatible FDSOI design architectureDHONG SANG HOO·Filed 2012·Granted May 14, 2013·27 cites·20 claims
- 3393US8418111B2Method and apparatus for achieving multiple patterning technology compliant design layoutCHEN HUANG-YU·Filed 2010·Granted Apr 9, 2013·29 cites·28 claims
- 3493US8255837B2Methods for cell boundary isolation in double patterning designLU LEE-CHUNG·Filed 2009·Granted Aug 28, 2012·19 cites·20 claims
- 3593US7808051B2Standard cell without OD space effect in Y-directionTAIWAN SEMICONDUCTOR MFG·Filed 2008·Granted Oct 5, 2010·29 cites·21 claims
- 3692US10685982B2Semiconductor structureTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2018·Granted Jun 16, 2020·6 cites·20 claims
- 3792US10686428B2Cell of transmission gate free circuit and integrated circuit layout including the sameTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2018·Granted Jun 16, 2020·5 cites·20 claims
- 3892US9887698B2Internal clock gated cellTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2015·Granted Feb 6, 2018·10 cites·20 claims
- 3992US8813016B1Multiple via connections using connectivity ringsTAIWAN SEMICONDUCTOR MFG·Filed 2013·Granted Aug 19, 2014·15 cites·20 claims
- 4092US8504972B2Standard cells having flexible layout architecture/boundariesHOU YUNG-CHIN·Filed 2010·Granted Aug 6, 2013·21 cites·19 claims
- 4192US7821039B2Layout architecture for improving circuit performanceTAIWAN SEMICONDUCTOR MFG·Filed 2008·Granted Oct 26, 2010·30 cites·29 claims
- 4291US11281836B2Cell structures and semiconductor devices having sameTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2021·Granted Mar 22, 2022·2 cites·20 claims
- 4391US10740531B2Integrated circuit, system for and method of forming an integrated circuitTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2017·Granted Aug 11, 2020·5 cites·20 claims
- 4491US10664565B2Method and system of expanding set of standard cells which comprise a libraryTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2018·Granted May 26, 2020·5 cites·20 claims
- 4591US10270432B2Flip-flop with delineated layout for reduced footprintTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2017·Granted Apr 23, 2019·5 cites·20 claims
- 4691US9356583B2Flip-flop circuitTAIWAN SEMICONDUCTOR MFG·Filed 2014·Granted May 31, 2016·7 cites·19 claims
- 4791US8350330B2Dummy pattern design for reducing device performance driftTAIWAN SEMICONDUCTOR MFG·Filed 2011·Granted Jan 8, 2013·7 cites·16 claims
- 4891US8239806B2Routing system and method for double patterning technologyCHEN HUANG-YU·Filed 2009·Granted Aug 7, 2012·27 cites·19 claims
- 4990US10530345B2Flip-flop with delineated layout for reduced footprintTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2019·Granted Jan 7, 2020·4 cites·20 claims
- 5090US10157840B2Integrated circuit having a high cell densityTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2017·Granted Dec 18, 2018·5 cites·20 claims
Showing the top 50 of 228 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →