Inventor

CHATTERJEE PALLAB K

38 patents

⚠️ This page may combine multiple inventors who share the name “CHATTERJEE PALLAB K”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

CHATTERJEE PALLAB K

TEXAS INSTRUMENTS INC

DRAM Cell with trench capacitor and vertical channel in substrate

Vertical DRAM cell and method

Method of making semiconductor having improved interlevel conductor insulation

Vertical DRAM cell and method

Method of fabricating an integrated circuit with metal interconnecting layers above and below active circuitry

Vertical inverter

High density micropackage for IC chips

Self-aligned stacked CMOS

High performance submicron metal-oxide-semiconductor field effect transistor device structure

Fabrication methods for the high capacity ram cell

Orthogonal chip mount system module and method

Integrated circuit with metal interconnecting layers above and below active circuitry

dRAM cell and array

Semiconductor device having improved interlevel conductor insulation

Taper isolated random access memory array and method of operating

Semiconductor device having a high breakdown voltage junction characteristic

Vertical inverter circuit

Method of making vertical inverter

Post-metal ion implant programmable MOS read only memory

Static random access memory with asynchronous power-down

Post-metal electron beam programmable MOS read only memory

Buried sense line V-groove MOS random access memory

Method of making post-metal ion beam programmable MOS read only memory

Dual plane well-type two-phase ccd

Dual plane barrier-type two-phase CCD

Semiconductor having improved interlevel conductor insulation

Memory with configuration RAM

Non-coplanar barrier-type charge coupled device with enhanced storage capacity and reduced leakage current

Co-planar barrier-type charge coupled device with enhanced storage capacity and decreased leakage current

Taper isolated ram cell without gate oxide

Buried storage punch through dynamic ram cell

MOS ram cell having improved refresh time

Co-planar well-type charge coupled device with enhanced storage capacity and reduced leakage current

I2 TECHNOLOGIES US INC

Data management system providing a data thesaurus for mapping between multiple data schemas or between multiple domains within a data schema

System and method for service transaction brokering among distributed marketplaces

System and method for providing electronic financial transaction services

RANGADASS VASUDEV

Data management system providing a data thesaurus for mapping between multiple data schemas or between multiple domains within a data schema

CHATTERJEE PALLAB K

Business-to-business internet infrastructure