Orthogonal chip mount system module and method

Abstract

An orthogonal chip mount system module (10) comprising a base module (12), an interconnect chip (14), orthogonal slots (16) and semiconductotr chips (18) is provided. The interconnect chip (14) is fixed to the base module (12) by high thermal conductivity epoxy. The semiconductor chips (18) are interference fitted into the slots (16). Solder pads (20) on the semiconductor chips (18) are aligned with solder pads (22) on the interconnect chip (14) and the system module (10) is then heated to the reflow temperature of the solder forming joints (24).

What is claimed is: 
     
       1. Apparatus for mounting semiconductor chips to form a system module, comprising a base module and means for interconnecting circuits on the semiconductor chips to said base module so that the chips and said base module form an integrated system module, said base module including orthogonal slots for receiving the semiconductor chips and further including a base portion and at least one interconnect chip fixed to said base portion, said interconnect chip having cutouts corresponding to said slots on said base module. 
     
     
       2. The apparatus of claim 1, wherein said interconnect chip comprises silicon coated with silicon dioxide. 
     
     
       3. The apparatus of claim 1, wherein said base portion comprises silicon. 
     
     
       4. The apparatus of claim 1, wherein said base portion comprises graphite coated with silicon carbide. 
     
     
       5. The apparatus of claim 1, wherein said means for interconnecting comprises: input/output solder pads on said interconnect chip;   input/output connectors on said interconnect chip to allow connection to an electronic device;   input/output solder pads on the semiconductor chips;   interconnect lines on said interconnect chip between said solder pads on said interconnect chip and said connectors on said interconnect chip; and   joints formed by aligning said solder pads on said interconnect chip with said solder pads on the semiconductor chips such that electrical continuity is formed from the semiconductor chips to the interconnect chip.   
     
     
       6. An improved semiconductor chip system module comprising a plurality of semiconductor chips having the same or different sizes, each having electrical devices formed thereon,   a base module and means for electrically connecting circuits on said semiconductor chips to said base module to provide a system module,   said base module including dimensions of length, width and depth and further including:   orthogonal slots perpendicular to said length and parallel to said width machined into said base module and dimensioned to receive said chips to maintain said chips within said module in a parallel configuration;   a base section having a top and a bottom surface; and   an interconnect chip attached to at least said top surface of said base section,   said interconnect chip having windows formed therethrough to correspond with said orthogonal slots.   
     
     
       7. The improved semiconductor system module of claim 6, wherein said base section comprises silicon. 
     
     
       8. The improved semiconductor system module of claim 6, wherein said base section comprises graphite coated with silicon carbide. 
     
     
       9. The improved semiconductor system module of claim 6, wherein said interconnect chip comprises silicon coated with silicon carbide. 
     
     
       10. The improved semiconductor system module of claim 6, wherein said interconnect chip comprises silicon coated with a diamond loaded compound. 
     
     
       11. The improved semiconductor system module of claim 6, wherein said base section comprises silicon coated with a high thermal conductivity material. 
     
     
       12. The improved semiconductor system module of claim 11, wherein said material comprises silicon carbide. 
     
     
       13. The improved semiconductor system module of claim 11, wherein said material comprises a diamond loaded compound. 
     
     
       14. The improved semiconductor system module of claim 6, wherein said interconnect chip comprises silicon coated with silicon dioxide. 
     
     
       15. The improved semiconductor system module of claim 14, wherein said silicon dioxide is further coated with silicon carbide. 
     
     
       16. The improved semiconductor system module of claim 14, wherein said silicon dioxide is further coated with a diamond loaded compound. 
     
     
       17. A method of forming an improved semiconductor chip system module, comprising the steps of: forming a base module with electrical conductors thereon, said base module forming   comprising forming a base portion, forming an interconnect chip having windows therethrough to match said orthogonal slots, forming input/output solder pads on said interconnect chip, and fixing said interconnect chip to said base portion;   machining orthogonal slots into said base module;   inserting semiconductor chips into said slots; and   soldering circuits on the semiconductor chips to said electrical conductors on said base module to form an integral semiconductor chip system module.   
     
     
       18. The method of claim 17, wherein the step of forming an interconnect chip comprises: covering a silicon chip with silicon dioxide;   patterning said silicon dioxide to match said orthogonal slots;   immersing said silicon chip in a potassium hydroxide/water solution to eat through said silicon chip; and   back grinding any remaining silicon and silicon dioxide in said pattern to form openings through said silicon chip.   
     
     
       19. The method of claim 17, wherein the step of soldering the semiconductor chips onto said base module comprises: forming input/output solder pads on the semiconductor chips corresponding to said input/output solder pads on said interconnect chip;   matching said input/output solder pads on said interconnect chip to said input/output solder pads on the semiconductor chips; and   reflowing said solder to form a joint between said interconnect chip and the semiconductor chips.   
     
     
       20. The method of claim 17, wherein the step of fixing said interconnect chip to said base portion comprises gluing said interconnect chip to said base portion.