Inventor

KRISHNAMURTHY RAM K

US84 patents

⚠️ This page may combine multiple inventors who share the name “KRISHNAMURTHY RAM K”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

KRISHNAMURTHY RAM K

INTEL CORP

Domino circuits with high performance and high noise immunity

Variable precision floating point multiply-add circuit

Apparatus and method for low power fully-interruptible latches and master-slave flip-flops

Multiple voltage mode pre-charging and selective level shifting

Hybrid CVSL pass-gate level-converting sequential circuit for multi-Vcc microprocessors

Low-power search line circuit encoding technique for content addressable memories

Static random access memory with symmetric leakage-compensated bit line

Full-swing source-follower leakage tolerant dynamic logic

Single ended interconnect systems

Dynamic threshold source follower voltage driver circuit

Dynamic logic with adaptive keeper

Low clock swing latch for dual-supply voltage design

Multi-phase clock generation and synchronization

Level converting latch

Leakage-tolerant keeper with dual output generation capability for deep sub-micron wide domino gates

Noise tolerant wide-fanin domino circuits

Pseudo-static leakage-tolerant register file bit-cell circuit

Single ended domino compatible dual function generator circuits

Tristate driver for integrated circuit interconnects

Reference-free single ended clocked sense amplifier circuit

Wide voltage range level shifter with symmetrical switching

Apparatus and method for low power fully-interruptible latches and master-slave flip-flops

Method, apparatus and system for a source-synchronous circuit-switched network on a chip (NOC)

Ultra low voltage and minimum operating voltage tolerant register file

Voltage-level converter

Low leakage and leakage tolerant stack free multi-ported register file

Soft error resistant circuits

Low switching activity dynamic driver for high performance interconnects

Shared keeper and footer flip-flop

Integrated clock gate circuit with embedded NOR

Shared keeper and footer flip-flop

Differential charge transfer sense amplifier

Noise tolerant wide-fanin domino circuits

Combined guaranteed throughput and best effort network-on-chip

High-performance adder

Conditional burn-in keeper for dynamic circuits

Current leakage reduction for loaded bit-lines in on-chip memory structures

Current leakage reduction for loaded bit-lines in on-chip memory structures

Current leakage reduction for loaded bit-lines in on-chip memory structures

Current leakage reduction for loaded bit-lines in on-chip memory structures

Variable virtual ground domino logic with leakage control

Neuromorphic computer with reconfigurable memory mapping for various neural network topologies

Neural network with reconfigurable sparse connectivity and online learning

Time borrowing flip-flop with clock gating scan multiplexer

MATHEW SANU K

Using dark bits to reduce physical unclonable function (PUF) error rate without storing dark bits location

On-the-fly key generation for encryption and decryption

HSU STEVEN K

Apparatus and method for low power fully-interruptible latches and master-slave flip-flops

UNIV CARNEGIE MELLON

Multiple power supply circuit architecture

SRINIVASAN SURESH

Split path multiply accumulate unit

SATPATHY SUDHIR K

Hybrid CAM assisted deflate decompression accelerator