Leakage-tolerant keeper with dual output generation capability for deep sub-micron wide domino gates

Abstract

A circuit including a clock signal input to receive a clock signal, at least one data signal input to receive at least one data signal, and a multiple input conditional inverter to receive the clock signal and the data signal, and to generate a dynamic output. The circuit also includes a conditional keeper circuit to charge a dynamic output node when the clock is evaluating and the dynamic output is high.

We claim:  
     
       1. A circuit comprising: 
       a clock signal input to receive a clock signal;  
       at least one data signal input to receive at least one data signal;  
       a dynamic output coupled to the clock signal input and the at least one data signal input; and  
       a conditional keeper circuit, coupled to the dynamic output, to hold a first gain rate on the dynamic output whenever the circuit is in an evaluating mode and the dynamic output is at a high logic level, and to hold a second gain rate on the dynamic output whenever the circuit is in the evaluating mode and the dynamic output is transitioning from the high logic level to a low logic level.  
     
     
       2. The circuit of  claim 1  further comprising an inverter to invert the dynamic output. 
     
     
       3. The circuit of  claim 2  wherein the conditional keeper circuit comprises: 
       a delay element having an input to receive the clock signal and an output,  
       a NAND gate having a first input to receive the output of the delay element, a second input to receive the dynamic output and an output; and  
       a first p-type transistor having a source connected to a positive supply voltage, a drain connected to the dynamic output node and a gate coupled to the output of the NAND gate; and  
       a second p-type transistor having a source connected to a positive supply voltage, a drain connected to the dynamic output node and a gate coupled to the inverter.  
     
     
       4. The circuit of  claim 3  wherein the first p-type transistor and the second p-type transistor are activated whenever the circuit is operating in the pre-charge mode. 
     
     
       5. The circuit of  claim 3  wherein the first p-type transistor is de-activated and the second p-type transistor is activated whenever the circuit transitions from the pre-charge mode to the evaluating mode. 
     
     
       6. The circuit of  claim 5  wherein the first p-type transistor and the second p-type transistor are de-activated whenever the circuit is operating in the evaluating mode and the dynamic output is at a low level. 
     
     
       7. The circuit of  claim 5  wherein the first p-type transistor is de-activated and the second p-type transistor are activated whenever the circuit is operating in the evaluating mode and the dynamic output is at a high level. 
     
     
       8. The circuit of  claim 3  further comprising a second inverter having an input coupled to the output of the NAND gate and an output, the second inverter to generate a second output. 
     
     
       9. The circuit of  claim 2 , wherein the conditional keeper circuit comprises: 
       a first delay element having an input to receive the clock signal and an output,  
       a second delay element having an input to receive the output of the first delay element and an output;  
       a NAND gate having a first input to receive the output of the second delay element, a second input to receive the dynamic output and an output;  
       a first p-type transistor having a source connected to a positive supply voltage, a drain connected to the dynamic output node and a gate coupled to the output of the first delay element; and  
       a second p-type transistor having a source connected to a positive supply voltage, a drain connected to the dynamic output node and a gate coupled to the output of the NAND gate; and  
       a third p-type transistor having a source connected to a positive supply voltage, a drain connected to the dynamic output node and a gate coupled to the inverter.  
     
     
       10. The circuit of  claim 9  wherein the first p-type transistor, the second p-type transistor and the third p-type transistor are activated whenever the conditional keeper holds a high gain on the dynamic output. 
     
     
       11. The circuit of  claim 9  wherein the first p-type transistor is de-activated and the second p-type transistor is activated whenever the conditional keeper holds a low gain on the dynamic output. 
     
     
       12. The circuit of  claim 11  wherein the first p-type transistor is de-activated and the second and third p-type transistors are activated whenever the circuit is operating in the evaluating mode and the dynamic output is at a high level. 
     
     
       13. The circuit of  claim 11  wherein the first, second and third p-type transistors are de-activated whenever the circuit is operating in the evaluating mode and the dynamic output is at a low level. 
     
     
       14. The circuit of  claim 9  further comprising a second inverter having an input coupled to the output of the NAND gate and an output, the second inverter to generate a second output. 
     
     
       15. A method comprising: 
       receiving an input signal;  
       receiving a low clock signal to generate a dynamic output;  
       driving the dynamic output to a high level at a first gain rate with a conditional keeper circuit whenever the input signal is at a low logic level; and  
       driving the dynamic output to a high level at a second gain rate with the conditional keeper circuit whenever the input signal is at a high logic level.  
     
     
       16. The method of  claim 15  further comprising driving the dynamic output to a low level with a logic circuit whenever the input signal is at a low logic level. 
     
     
       17. The method of  claim 15  further comprising inverting the dynamic output to generate a first output. 
     
     
       18. A conditional keeper circuit comprising: 
       a delay element having an input to receive a clock signal and an output;  
       a NAND gate having a first input to receive the output of the delay element, a second input to receive a dynamic output node and an output;  
       a first p-type transistor having a source connected to a positive supply voltage, a drain connected to the dynamic output node and a gate coupled to the output of the NAND gate;  
       an inverter to coupled to the dynamic output node to invert a dynamic output signal; and  
       a second p-type transistor including a source connected to a positive power supply voltage, a drain coupled to the dynamic output node, and a gate coupled to the output of the inverter;  
       wherein the conditional keeper holds a first gain rate on the dynamic output during an evaluating mode whenever the dynamic output node is at a high logic level, and holds a second gain rate on the dynamic output node during the evaluating mode whenever the dynamic output is transitioning from the high logic level to a low logic level.  
     
     
       19. The circuit of  claim 18  further comprising a second inverter having an input coupled to the output of the NAND gate and an output. 
     
     
       20. The circuit of  claim 18  wherein the delay element comprises a first delay element including an input to receive the clock signal and an output, and a second delay element to receive the output of the first delay element and an output coupled to the first input of the NAND gate, and the circuit further comprises: 
       a third p-type transistor having a source connected to a positive supply voltage, a drain connected to the dynamic output node and a gate coupled to the output of the first delay element.  
     
     
       21. The circuit of  claim 20  wherein the first p-type transistor, the second p-type transistor and the third p-type transistor are activated whenever the conditional keeper holds a high gain on the dynamic output. 
     
     
       22. The circuit of  claim 20  wherein the first p-type transistor is de-activated and the second p-type transistor is activated whenever the conditional keeper holds a low gain on the dynamic output. 
     
     
       23. The circuit of  claim 22  wherein the first p-type transistor is de-activated and the second and third p-type transistors are activated during the evaluating mode whenever the dynamic output is at a high level. 
     
     
       24. The circuit of  claim 22  wherein the first, second and third p-type transistors are de-activated during the evaluating mode whenever the dynamic output is at a low level.