Inventor

SOUMYANATH KRISHNAMURTHY

US41 patents

⚠️ This page may combine multiple inventors who share the name “SOUMYANATH KRISHNAMURTHY”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

SOUMYANATH KRISHNAMURTHY

INTEL CORP

Differential circuits employing forward body bias

Single event upset hardened latch

Domino circuits with high performance and high noise immunity

Single event upset hardened latch

Device and method of quadrature oscillation

Quadrature oscillator and methods thereof

Transformer coupled quadrature tuned oscillator

Single ended interconnect systems

Low voltage PVT insensitive MOSFET based voltage reference circuit

Nonlinear body effect compensated MOSFET voltage reference

Low loss interconnect structure for use in microelectronic circuits

Leakage-tolerant keeper with dual output generation capability for deep sub-micron wide domino gates

Boosted multiplexer transmission gate

Self-tuning amplifier

Single ended domino compatible dual function generator circuits

Transceiver with calibrated I and Q paths and methods for deconvolved calibration

Adaptively extending tunable range of frequency in a closed loop

Differential, mixed swing, tristate driver circuit for high performance and low power on-chip interconnects

Digital outphasing transmitter architecture

Hierarchical clock grid for on-die salphasic clocking

Soft error rate tolerant latch

Digital transmitter and methods of generating radio-frequency signals using time-domain outphasing

Method and apparatus for obtaining linear code-delay response from area-efficient delay cells

Quadrature oscillator and methods thereof

Leakage-tolerant circuit and method for large register files

Strained-silicon voltage controlled oscillator (VCO)

Discrete time filter having gain for digital sampling receivers

System and method for controlling resonance frequency of film bulk acoustic resonator devices

Low loss interconnect structure for use in microelectronic circuits

Adaptively extending tunable range of frequency in a closed loop

Clock receiver circuit for on-die salphasic clocking

Clock receiver circuit for on-die salphasic clocking

Variable gain amplifier with direct current offset correction

Area efficient waveform evaluation and DC offset cancellation circuits

Area efficient waveform evaluation and DC offset cancellation circuits

Filter with gain

Method and apparatus to combine radio frequency signals

Fast dual-rail dynamic logic style

Flash [II]-Domino: a fast dual-rail dynamic logic style

Reference impedance apparatus, systems, and methods

VERHELST MARIAN K

Programmable engine having a reconfigurable accelerator data path for testing and calibration of analog front ends in radio devices