Inventor

COHN JOHN M

US66 patents

⚠️ This page may combine multiple inventors who share the name “COHN JOHN M”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

COHN JOHN M

IBM

Use of redundant routes to increase the yield and reliability of a VLSI layout

Circuit layout methodology using a shape processing application

Object placement aid

Method of adding fabrication monitors to integrated circuit chips

Physical design system and method

Concurrent logical and physical construction of voltage islands for mixed supply voltage designs

Hierarchical layout method for integrated circuits

Method for supply voltage drop analysis during placement phase of chip design

Method of integrated circuit design checking using progressive individual network analysis

System and method for inserting leakage reduction control in logic circuits

Simplified tiling pattern method

Method for adding decoupling capacitance during integrated circuit design

Method of integrated circuit design by selection of noise tolerant gates

Contextual based groundrule compensation method of mask data set generation

Designing scan chains with specific parameter sensitivities to identify process defects

Autonomous decentralized peer-to-peer telemetry

Pattern-matching for transistor level netlists

System and method of providing error detection and correction capability in an integrated circuit using redundant logic cells of an embedded FPGA

Method for designing an integrated circuit defect monitor

Circuit and method for monitoring defects

Multiple supply gate array backfill structure

Integrated circuit diagnosing method, system, and program product

System and method of providing error detection and correction capability in an integrated circuit using redundant logic cells of an embedded FPGA

Power reduction by stage in integrated circuit

Circuit layout methodology using via shape process

Utilizing clock shield as defect monitor

Sensor based context augmentation of search queries

Sensor based context augmentation of search queries

Power switch circuit sizing technique

Learning based logic diagnosis

Device self-servicing in an autonomous decentralized peer-to-peer environment

Endpoint load rebalancing controller

Endpoint load rebalancing controller

Method and apparatus for manufacturing diamond shaped chips

Method of switching voltage islands in integrated circuits when a grid voltage at a reference location is within a specified range

Methods for designing a product chip a priori for design subsetting, feature analysis, and yield learning

Method of adding fabrication monitors to integrated circuit chips

Method of adding fabrication monitors to integrated circuit chips

Utilizing clock shield as defect monitor

Optical Proximity Correction Structures Having Decoupling Capacitors

Wiring optimizations for power

COHN JOHN M

Methods for reading a feature pattern from a packaged die

Fabricating product chips and die with a feature pattern that contains information relating to the product chip

Physical design system and method

Physical design system and method

Acoustic diagnosis and correction system

Acoustic diagnosis and correction system

Method of distributing a random variable using statistically correct spatial interpolation continuously with spatially inhomogeneous statistical correlation versus distance, standard deviation, and mean

Method for IC wiring yield optimization, including wire widening during and after routing

Product chips and die with a feature pattern that contains information relating to the product chip